// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
// Date        : Thu Mar 20 17:26:32 2025
// Host        : Kvn running 64-bit major release  (build 9200)
// Command     : write_verilog -mode funcsim -nolib -force -file
//               D:/Vivado/project_SystolicArray/project_SystolicArray.sim/sim_1/synth/func/xsim/TB_systolic_array_func_synth.v
// Design      : systolic_array
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a35tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module pe
   (Q,
    \right_out_reg[3]_0 ,
    DI,
    \right_out_reg[3]_1 ,
    S,
    \bottom_out_reg[3]_0 ,
    \bottom_out_reg[1]_0 ,
    \bottom_out_reg[1]_1 ,
    \bottom_out_reg[1]_2 ,
    \psum_reg[7]_0 ,
    \right_out_reg[2]_0 ,
    \bottom_out_reg[2]_0 ,
    \bottom_out_reg[1]_3 ,
    \right_out_reg[3]_2 ,
    \bottom_out_reg[2]_1 ,
    \right_out_reg[2]_1 ,
    \bottom_out_reg[3]_1 ,
    \right_out_reg[1]_0 ,
    \right_out_reg[0]_0 ,
    \bottom_out_reg[0]_0 ,
    product__1_carry__0_i_5__0_0,
    product__1_carry__0_i_5__0_1,
    product__1_carry__0_i_5__0_2,
    product__1_carry_0,
    product__1_carry__0_0,
    product__1_carry__0_i_5__2_0,
    product__1_carry_1,
    product__1_carry_2,
    CO,
    \result[0][1] ,
    SR,
    CLK);
  output [7:0]Q;
  output [3:0]\right_out_reg[3]_0 ;
  output [2:0]DI;
  output [2:0]\right_out_reg[3]_1 ;
  output [3:0]S;
  output [3:0]\bottom_out_reg[3]_0 ;
  output [2:0]\bottom_out_reg[1]_0 ;
  output [2:0]\bottom_out_reg[1]_1 ;
  output [3:0]\bottom_out_reg[1]_2 ;
  output [0:0]\psum_reg[7]_0 ;
  output [2:0]\right_out_reg[2]_0 ;
  output [2:0]\bottom_out_reg[2]_0 ;
  input \bottom_out_reg[1]_3 ;
  input \right_out_reg[3]_2 ;
  input \bottom_out_reg[2]_1 ;
  input \right_out_reg[2]_1 ;
  input \bottom_out_reg[3]_1 ;
  input \right_out_reg[1]_0 ;
  input \right_out_reg[0]_0 ;
  input \bottom_out_reg[0]_0 ;
  input product__1_carry__0_i_5__0_0;
  input product__1_carry__0_i_5__0_1;
  input product__1_carry__0_i_5__0_2;
  input product__1_carry_0;
  input product__1_carry__0_0;
  input product__1_carry__0_i_5__2_0;
  input product__1_carry_1;
  input product__1_carry_2;
  input [0:0]CO;
  input [0:0]\result[0][1] ;
  input [0:0]SR;
  input CLK;

  wire CLK;
  wire [0:0]CO;
  wire [2:0]DI;
  wire [7:0]Q;
  wire [3:0]S;
  wire [0:0]SR;
  wire \bottom_out_reg[0]_0 ;
  wire [2:0]\bottom_out_reg[1]_0 ;
  wire [2:0]\bottom_out_reg[1]_1 ;
  wire [3:0]\bottom_out_reg[1]_2 ;
  wire \bottom_out_reg[1]_3 ;
  wire [2:0]\bottom_out_reg[2]_0 ;
  wire \bottom_out_reg[2]_1 ;
  wire [3:0]\bottom_out_reg[3]_0 ;
  wire \bottom_out_reg[3]_1 ;
  wire [7:0]product;
  wire product__1_carry_0;
  wire product__1_carry_1;
  wire product__1_carry_2;
  wire product__1_carry__0_0;
  wire product__1_carry__0_i_10__0_n_0;
  wire product__1_carry__0_i_10__2_n_0;
  wire product__1_carry__0_i_10_n_0;
  wire product__1_carry__0_i_1_n_0;
  wire product__1_carry__0_i_2_n_0;
  wire product__1_carry__0_i_3_n_0;
  wire product__1_carry__0_i_4_n_0;
  wire product__1_carry__0_i_5__0_0;
  wire product__1_carry__0_i_5__0_1;
  wire product__1_carry__0_i_5__0_2;
  wire product__1_carry__0_i_5__2_0;
  wire product__1_carry__0_i_5_n_0;
  wire product__1_carry__0_i_6_n_0;
  wire product__1_carry__0_i_7__0_n_0;
  wire product__1_carry__0_i_7__2_n_0;
  wire product__1_carry__0_i_7_n_0;
  wire product__1_carry__0_i_8__0_n_0;
  wire product__1_carry__0_i_8__2_n_0;
  wire product__1_carry__0_i_8_n_0;
  wire product__1_carry__0_i_9__0_n_0;
  wire product__1_carry__0_i_9__2_n_0;
  wire product__1_carry__0_i_9_n_0;
  wire product__1_carry__0_n_2;
  wire product__1_carry__0_n_3;
  wire product__1_carry_i_1_n_0;
  wire product__1_carry_i_2_n_0;
  wire product__1_carry_i_3_n_0;
  wire product__1_carry_i_4_n_0;
  wire product__1_carry_i_5_n_0;
  wire product__1_carry_i_6_n_0;
  wire product__1_carry_i_7_n_0;
  wire product__1_carry_i_8__0_n_0;
  wire product__1_carry_i_8__2_n_0;
  wire product__1_carry_i_8_n_0;
  wire product__1_carry_n_0;
  wire product__1_carry_n_1;
  wire product__1_carry_n_2;
  wire product__1_carry_n_3;
  wire [7:0]psum0;
  wire psum0_carry__0_i_1_n_0;
  wire psum0_carry__0_i_2_n_0;
  wire psum0_carry__0_i_3_n_0;
  wire psum0_carry__0_i_4_n_0;
  wire psum0_carry__0_n_1;
  wire psum0_carry__0_n_2;
  wire psum0_carry__0_n_3;
  wire psum0_carry_i_1_n_0;
  wire psum0_carry_i_2_n_0;
  wire psum0_carry_i_3_n_0;
  wire psum0_carry_i_4_n_0;
  wire psum0_carry_n_0;
  wire psum0_carry_n_1;
  wire psum0_carry_n_2;
  wire psum0_carry_n_3;
  wire [0:0]\psum_reg[7]_0 ;
  wire [0:0]\result[0][1] ;
  wire \right_out_reg[0]_0 ;
  wire \right_out_reg[1]_0 ;
  wire [2:0]\right_out_reg[2]_0 ;
  wire \right_out_reg[2]_1 ;
  wire [3:0]\right_out_reg[3]_0 ;
  wire [2:0]\right_out_reg[3]_1 ;
  wire \right_out_reg[3]_2 ;
  wire [2:2]NLW_product__1_carry__0_CO_UNCONNECTED;
  wire [3:3]NLW_product__1_carry__0_O_UNCONNECTED;
  wire [3:3]NLW_psum0_carry__0_CO_UNCONNECTED;

  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[0]_0 ),
        .Q(\bottom_out_reg[3]_0 [0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[1]_3 ),
        .Q(\bottom_out_reg[3]_0 [1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[2]_1 ),
        .Q(\bottom_out_reg[3]_0 [2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[3]_1 ),
        .Q(\bottom_out_reg[3]_0 [3]),
        .R(SR));
  CARRY4 product__1_carry
       (.CI(1'b0),
        .CO({product__1_carry_n_0,product__1_carry_n_1,product__1_carry_n_2,product__1_carry_n_3}),
        .CYINIT(1'b0),
        .DI({product__1_carry_i_1_n_0,product__1_carry_i_2_n_0,product__1_carry_i_3_n_0,1'b0}),
        .O(product[3:0]),
        .S({product__1_carry_i_4_n_0,product__1_carry_i_5_n_0,product__1_carry_i_6_n_0,product__1_carry_i_7_n_0}));
  CARRY4 product__1_carry__0
       (.CI(product__1_carry_n_0),
        .CO({product[7],NLW_product__1_carry__0_CO_UNCONNECTED[2],product__1_carry__0_n_2,product__1_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,product__1_carry__0_i_1_n_0,product__1_carry__0_i_2_n_0,product__1_carry__0_i_3_n_0}),
        .O({NLW_product__1_carry__0_O_UNCONNECTED[3],product[6:4]}),
        .S({1'b1,product__1_carry__0_i_4_n_0,product__1_carry__0_i_5_n_0,product__1_carry__0_i_6_n_0}));
  LUT6 #(
    .INIT(64'hFC88800080000000)) 
    product__1_carry__0_i_1
       (.I0(\bottom_out_reg[1]_3 ),
        .I1(\right_out_reg[3]_2 ),
        .I2(\right_out_reg[1]_0 ),
        .I3(\bottom_out_reg[3]_1 ),
        .I4(\bottom_out_reg[2]_1 ),
        .I5(\right_out_reg[2]_1 ),
        .O(product__1_carry__0_i_1_n_0));
  LUT6 #(
    .INIT(64'hF880880080800000)) 
    product__1_carry__0_i_10
       (.I0(\right_out_reg[2]_1 ),
        .I1(\bottom_out_reg[1]_3 ),
        .I2(\right_out_reg[1]_0 ),
        .I3(\bottom_out_reg[3]_1 ),
        .I4(\bottom_out_reg[2]_1 ),
        .I5(\right_out_reg[0]_0 ),
        .O(product__1_carry__0_i_10_n_0));
  LUT6 #(
    .INIT(64'hF880880080800000)) 
    product__1_carry__0_i_10__0
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__0_0),
        .I2(\right_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__0_2),
        .I4(product__1_carry__0_i_5__0_1),
        .I5(\right_out_reg[3]_0 [0]),
        .O(product__1_carry__0_i_10__0_n_0));
  LUT6 #(
    .INIT(64'hF880880080800000)) 
    product__1_carry__0_i_10__2
       (.I0(product__1_carry__0_i_5__2_0),
        .I1(\bottom_out_reg[3]_0 [1]),
        .I2(product__1_carry_1),
        .I3(\bottom_out_reg[3]_0 [3]),
        .I4(\bottom_out_reg[3]_0 [2]),
        .I5(product__1_carry_2),
        .O(product__1_carry__0_i_10__2_n_0));
  LUT6 #(
    .INIT(64'hFC88800080000000)) 
    product__1_carry__0_i_1__0
       (.I0(product__1_carry__0_i_5__0_0),
        .I1(\right_out_reg[3]_0 [3]),
        .I2(\right_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__0_2),
        .I4(product__1_carry__0_i_5__0_1),
        .I5(\right_out_reg[3]_0 [2]),
        .O(\right_out_reg[3]_1 [2]));
  LUT6 #(
    .INIT(64'hFC88800080000000)) 
    product__1_carry__0_i_1__2
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_0),
        .I2(product__1_carry_1),
        .I3(\bottom_out_reg[3]_0 [3]),
        .I4(\bottom_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__2_0),
        .O(\bottom_out_reg[1]_1 [2]));
  LUT3 #(
    .INIT(8'h80)) 
    product__1_carry__0_i_2
       (.I0(\bottom_out_reg[0]_0 ),
        .I1(product__1_carry__0_i_7_n_0),
        .I2(\right_out_reg[3]_2 ),
        .O(product__1_carry__0_i_2_n_0));
  LUT3 #(
    .INIT(8'h80)) 
    product__1_carry__0_i_2__0
       (.I0(product__1_carry_0),
        .I1(product__1_carry__0_i_7__0_n_0),
        .I2(\right_out_reg[3]_0 [3]),
        .O(\right_out_reg[3]_1 [1]));
  LUT3 #(
    .INIT(8'h80)) 
    product__1_carry__0_i_2__2
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_7__2_n_0),
        .I2(product__1_carry__0_0),
        .O(\bottom_out_reg[1]_1 [1]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    product__1_carry__0_i_3
       (.I0(\right_out_reg[3]_2 ),
        .I1(\bottom_out_reg[1]_3 ),
        .I2(product__1_carry_i_8_n_0),
        .I3(\right_out_reg[0]_0 ),
        .I4(\bottom_out_reg[0]_0 ),
        .I5(product__1_carry__0_i_8_n_0),
        .O(product__1_carry__0_i_3_n_0));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    product__1_carry__0_i_3__0
       (.I0(\right_out_reg[3]_0 [3]),
        .I1(product__1_carry__0_i_5__0_0),
        .I2(product__1_carry_i_8__0_n_0),
        .I3(\right_out_reg[3]_0 [0]),
        .I4(product__1_carry_0),
        .I5(product__1_carry__0_i_8__0_n_0),
        .O(\right_out_reg[3]_1 [0]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    product__1_carry__0_i_3__2
       (.I0(product__1_carry__0_0),
        .I1(\bottom_out_reg[3]_0 [1]),
        .I2(product__1_carry_i_8__2_n_0),
        .I3(product__1_carry_2),
        .I4(\bottom_out_reg[3]_0 [0]),
        .I5(product__1_carry__0_i_8__2_n_0),
        .O(\bottom_out_reg[1]_1 [0]));
  LUT6 #(
    .INIT(64'h1777808088000000)) 
    product__1_carry__0_i_4
       (.I0(\right_out_reg[2]_1 ),
        .I1(\bottom_out_reg[2]_1 ),
        .I2(\right_out_reg[1]_0 ),
        .I3(\bottom_out_reg[1]_3 ),
        .I4(\right_out_reg[3]_2 ),
        .I5(\bottom_out_reg[3]_1 ),
        .O(product__1_carry__0_i_4_n_0));
  LUT6 #(
    .INIT(64'h1777808088000000)) 
    product__1_carry__0_i_4__0
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__0_1),
        .I2(\right_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__0_0),
        .I4(\right_out_reg[3]_0 [3]),
        .I5(product__1_carry__0_i_5__0_2),
        .O(\right_out_reg[2]_0 [2]));
  LUT6 #(
    .INIT(64'h1777808088000000)) 
    product__1_carry__0_i_4__2
       (.I0(product__1_carry__0_i_5__2_0),
        .I1(\bottom_out_reg[3]_0 [2]),
        .I2(product__1_carry_1),
        .I3(\bottom_out_reg[3]_0 [1]),
        .I4(product__1_carry__0_0),
        .I5(\bottom_out_reg[3]_0 [3]),
        .O(\bottom_out_reg[2]_0 [2]));
  LUT4 #(
    .INIT(16'h7F80)) 
    product__1_carry__0_i_5
       (.I0(\right_out_reg[3]_2 ),
        .I1(product__1_carry__0_i_7_n_0),
        .I2(\bottom_out_reg[0]_0 ),
        .I3(product__1_carry__0_i_9_n_0),
        .O(product__1_carry__0_i_5_n_0));
  LUT4 #(
    .INIT(16'h7F80)) 
    product__1_carry__0_i_5__0
       (.I0(\right_out_reg[3]_0 [3]),
        .I1(product__1_carry__0_i_7__0_n_0),
        .I2(product__1_carry_0),
        .I3(product__1_carry__0_i_9__0_n_0),
        .O(\right_out_reg[2]_0 [1]));
  LUT4 #(
    .INIT(16'h7F80)) 
    product__1_carry__0_i_5__2
       (.I0(product__1_carry__0_0),
        .I1(product__1_carry__0_i_7__2_n_0),
        .I2(\bottom_out_reg[3]_0 [0]),
        .I3(product__1_carry__0_i_9__2_n_0),
        .O(\bottom_out_reg[2]_0 [1]));
  LUT2 #(
    .INIT(4'h6)) 
    product__1_carry__0_i_6
       (.I0(product__1_carry__0_i_3_n_0),
        .I1(product__1_carry__0_i_10_n_0),
        .O(product__1_carry__0_i_6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    product__1_carry__0_i_6__0
       (.I0(\right_out_reg[3]_1 [0]),
        .I1(product__1_carry__0_i_10__0_n_0),
        .O(\right_out_reg[2]_0 [0]));
  LUT2 #(
    .INIT(4'h6)) 
    product__1_carry__0_i_6__2
       (.I0(\bottom_out_reg[1]_1 [0]),
        .I1(product__1_carry__0_i_10__2_n_0),
        .O(\bottom_out_reg[2]_0 [0]));
  LUT6 #(
    .INIT(64'h8000200000000000)) 
    product__1_carry__0_i_7
       (.I0(\right_out_reg[0]_0 ),
        .I1(\bottom_out_reg[3]_1 ),
        .I2(\bottom_out_reg[2]_1 ),
        .I3(\right_out_reg[1]_0 ),
        .I4(\right_out_reg[2]_1 ),
        .I5(\bottom_out_reg[1]_3 ),
        .O(product__1_carry__0_i_7_n_0));
  LUT6 #(
    .INIT(64'h8000200000000000)) 
    product__1_carry__0_i_7__0
       (.I0(\right_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_5__0_2),
        .I2(product__1_carry__0_i_5__0_1),
        .I3(\right_out_reg[3]_0 [1]),
        .I4(\right_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__0_0),
        .O(product__1_carry__0_i_7__0_n_0));
  LUT6 #(
    .INIT(64'h8000200000000000)) 
    product__1_carry__0_i_7__2
       (.I0(product__1_carry_2),
        .I1(\bottom_out_reg[3]_0 [3]),
        .I2(\bottom_out_reg[3]_0 [2]),
        .I3(product__1_carry_1),
        .I4(product__1_carry__0_i_5__2_0),
        .I5(\bottom_out_reg[3]_0 [1]),
        .O(product__1_carry__0_i_7__2_n_0));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry__0_i_8
       (.I0(\bottom_out_reg[1]_3 ),
        .I1(\right_out_reg[3]_2 ),
        .I2(\bottom_out_reg[2]_1 ),
        .I3(\right_out_reg[2]_1 ),
        .I4(\bottom_out_reg[3]_1 ),
        .I5(\right_out_reg[1]_0 ),
        .O(product__1_carry__0_i_8_n_0));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry__0_i_8__0
       (.I0(product__1_carry__0_i_5__0_0),
        .I1(\right_out_reg[3]_0 [3]),
        .I2(product__1_carry__0_i_5__0_1),
        .I3(\right_out_reg[3]_0 [2]),
        .I4(product__1_carry__0_i_5__0_2),
        .I5(\right_out_reg[3]_0 [1]),
        .O(product__1_carry__0_i_8__0_n_0));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry__0_i_8__2
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_0),
        .I2(\bottom_out_reg[3]_0 [2]),
        .I3(product__1_carry__0_i_5__2_0),
        .I4(\bottom_out_reg[3]_0 [3]),
        .I5(product__1_carry_1),
        .O(product__1_carry__0_i_8__2_n_0));
  LUT6 #(
    .INIT(64'hC4B470F04CCC8000)) 
    product__1_carry__0_i_9
       (.I0(\bottom_out_reg[1]_3 ),
        .I1(\right_out_reg[3]_2 ),
        .I2(\bottom_out_reg[3]_1 ),
        .I3(\right_out_reg[1]_0 ),
        .I4(\bottom_out_reg[2]_1 ),
        .I5(\right_out_reg[2]_1 ),
        .O(product__1_carry__0_i_9_n_0));
  LUT6 #(
    .INIT(64'hC4B470F04CCC8000)) 
    product__1_carry__0_i_9__0
       (.I0(product__1_carry__0_i_5__0_0),
        .I1(\right_out_reg[3]_0 [3]),
        .I2(product__1_carry__0_i_5__0_2),
        .I3(\right_out_reg[3]_0 [1]),
        .I4(product__1_carry__0_i_5__0_1),
        .I5(\right_out_reg[3]_0 [2]),
        .O(product__1_carry__0_i_9__0_n_0));
  LUT6 #(
    .INIT(64'hC4B470F04CCC8000)) 
    product__1_carry__0_i_9__2
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_0),
        .I2(\bottom_out_reg[3]_0 [3]),
        .I3(product__1_carry_1),
        .I4(\bottom_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__2_0),
        .O(product__1_carry__0_i_9__2_n_0));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_1
       (.I0(\right_out_reg[2]_1 ),
        .I1(\bottom_out_reg[1]_3 ),
        .I2(\bottom_out_reg[3]_1 ),
        .I3(\right_out_reg[0]_0 ),
        .I4(\bottom_out_reg[2]_1 ),
        .I5(\right_out_reg[1]_0 ),
        .O(product__1_carry_i_1_n_0));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_1__0
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__0_0),
        .I2(product__1_carry__0_i_5__0_2),
        .I3(\right_out_reg[3]_0 [0]),
        .I4(product__1_carry__0_i_5__0_1),
        .I5(\right_out_reg[3]_0 [1]),
        .O(DI[2]));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_1__2
       (.I0(product__1_carry__0_i_5__2_0),
        .I1(\bottom_out_reg[3]_0 [1]),
        .I2(\bottom_out_reg[3]_0 [3]),
        .I3(product__1_carry_2),
        .I4(\bottom_out_reg[3]_0 [2]),
        .I5(product__1_carry_1),
        .O(\bottom_out_reg[1]_0 [2]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_2
       (.I0(\bottom_out_reg[1]_3 ),
        .I1(\right_out_reg[1]_0 ),
        .I2(\right_out_reg[0]_0 ),
        .I3(\bottom_out_reg[2]_1 ),
        .O(product__1_carry_i_2_n_0));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_2__0
       (.I0(product__1_carry__0_i_5__0_0),
        .I1(\right_out_reg[3]_0 [1]),
        .I2(\right_out_reg[3]_0 [0]),
        .I3(product__1_carry__0_i_5__0_1),
        .O(DI[1]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_2__2
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry_1),
        .I2(product__1_carry_2),
        .I3(\bottom_out_reg[3]_0 [2]),
        .O(\bottom_out_reg[1]_0 [1]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_3
       (.I0(\right_out_reg[1]_0 ),
        .I1(\bottom_out_reg[0]_0 ),
        .O(product__1_carry_i_3_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_3__0
       (.I0(\right_out_reg[3]_0 [1]),
        .I1(product__1_carry_0),
        .O(DI[0]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_3__2
       (.I0(product__1_carry_1),
        .I1(\bottom_out_reg[3]_0 [0]),
        .O(\bottom_out_reg[1]_0 [0]));
  LUT6 #(
    .INIT(64'h95556AAA6AAA6AAA)) 
    product__1_carry_i_4
       (.I0(product__1_carry_i_1_n_0),
        .I1(\bottom_out_reg[1]_3 ),
        .I2(product__1_carry_i_8_n_0),
        .I3(\right_out_reg[0]_0 ),
        .I4(\right_out_reg[3]_2 ),
        .I5(\bottom_out_reg[0]_0 ),
        .O(product__1_carry_i_4_n_0));
  LUT6 #(
    .INIT(64'h95556AAA6AAA6AAA)) 
    product__1_carry_i_4__0
       (.I0(DI[2]),
        .I1(product__1_carry__0_i_5__0_0),
        .I2(product__1_carry_i_8__0_n_0),
        .I3(\right_out_reg[3]_0 [0]),
        .I4(\right_out_reg[3]_0 [3]),
        .I5(product__1_carry_0),
        .O(S[3]));
  LUT6 #(
    .INIT(64'h95556AAA6AAA6AAA)) 
    product__1_carry_i_4__2
       (.I0(\bottom_out_reg[1]_0 [2]),
        .I1(\bottom_out_reg[3]_0 [1]),
        .I2(product__1_carry_i_8__2_n_0),
        .I3(product__1_carry_2),
        .I4(product__1_carry__0_0),
        .I5(\bottom_out_reg[3]_0 [0]),
        .O(\bottom_out_reg[1]_2 [3]));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_5
       (.I0(\bottom_out_reg[2]_1 ),
        .I1(\right_out_reg[0]_0 ),
        .I2(\right_out_reg[1]_0 ),
        .I3(\bottom_out_reg[1]_3 ),
        .I4(\bottom_out_reg[0]_0 ),
        .I5(\right_out_reg[2]_1 ),
        .O(product__1_carry_i_5_n_0));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_5__0
       (.I0(product__1_carry__0_i_5__0_1),
        .I1(\right_out_reg[3]_0 [0]),
        .I2(\right_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__0_0),
        .I4(product__1_carry_0),
        .I5(\right_out_reg[3]_0 [2]),
        .O(S[2]));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_5__2
       (.I0(\bottom_out_reg[3]_0 [2]),
        .I1(product__1_carry_2),
        .I2(product__1_carry_1),
        .I3(\bottom_out_reg[3]_0 [1]),
        .I4(\bottom_out_reg[3]_0 [0]),
        .I5(product__1_carry__0_i_5__2_0),
        .O(\bottom_out_reg[1]_2 [2]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_6
       (.I0(\bottom_out_reg[0]_0 ),
        .I1(\right_out_reg[1]_0 ),
        .I2(\bottom_out_reg[1]_3 ),
        .I3(\right_out_reg[0]_0 ),
        .O(product__1_carry_i_6_n_0));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_6__0
       (.I0(product__1_carry_0),
        .I1(\right_out_reg[3]_0 [1]),
        .I2(product__1_carry__0_i_5__0_0),
        .I3(\right_out_reg[3]_0 [0]),
        .O(S[1]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_6__2
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(product__1_carry_1),
        .I2(\bottom_out_reg[3]_0 [1]),
        .I3(product__1_carry_2),
        .O(\bottom_out_reg[1]_2 [1]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_7
       (.I0(\right_out_reg[0]_0 ),
        .I1(\bottom_out_reg[0]_0 ),
        .O(product__1_carry_i_7_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_7__0
       (.I0(\right_out_reg[3]_0 [0]),
        .I1(product__1_carry_0),
        .O(S[0]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_7__2
       (.I0(product__1_carry_2),
        .I1(\bottom_out_reg[3]_0 [0]),
        .O(\bottom_out_reg[1]_2 [0]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_8
       (.I0(\bottom_out_reg[2]_1 ),
        .I1(\right_out_reg[1]_0 ),
        .O(product__1_carry_i_8_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_8__0
       (.I0(product__1_carry__0_i_5__0_1),
        .I1(\right_out_reg[3]_0 [1]),
        .O(product__1_carry_i_8__0_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_8__2
       (.I0(\bottom_out_reg[3]_0 [2]),
        .I1(product__1_carry_1),
        .O(product__1_carry_i_8__2_n_0));
  CARRY4 psum0_carry
       (.CI(1'b0),
        .CO({psum0_carry_n_0,psum0_carry_n_1,psum0_carry_n_2,psum0_carry_n_3}),
        .CYINIT(1'b0),
        .DI(Q[3:0]),
        .O(psum0[3:0]),
        .S({psum0_carry_i_1_n_0,psum0_carry_i_2_n_0,psum0_carry_i_3_n_0,psum0_carry_i_4_n_0}));
  CARRY4 psum0_carry__0
       (.CI(psum0_carry_n_0),
        .CO({NLW_psum0_carry__0_CO_UNCONNECTED[3],psum0_carry__0_n_1,psum0_carry__0_n_2,psum0_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,Q[6:4]}),
        .O(psum0[7:4]),
        .S({psum0_carry__0_i_1_n_0,psum0_carry__0_i_2_n_0,psum0_carry__0_i_3_n_0,psum0_carry__0_i_4_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_1
       (.I0(product[7]),
        .I1(Q[7]),
        .O(psum0_carry__0_i_1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_1__0
       (.I0(CO),
        .I1(\result[0][1] ),
        .O(\psum_reg[7]_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_2
       (.I0(Q[6]),
        .I1(product[6]),
        .O(psum0_carry__0_i_2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_3
       (.I0(Q[5]),
        .I1(product[5]),
        .O(psum0_carry__0_i_3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_4
       (.I0(Q[4]),
        .I1(product[4]),
        .O(psum0_carry__0_i_4_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_1
       (.I0(Q[3]),
        .I1(product[3]),
        .O(psum0_carry_i_1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_2
       (.I0(Q[2]),
        .I1(product[2]),
        .O(psum0_carry_i_2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_3
       (.I0(Q[1]),
        .I1(product[1]),
        .O(psum0_carry_i_3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_4
       (.I0(Q[0]),
        .I1(product[0]),
        .O(psum0_carry_i_4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0[2]),
        .Q(Q[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0[3]),
        .Q(Q[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0[4]),
        .Q(Q[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0[5]),
        .Q(Q[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0[6]),
        .Q(Q[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0[7]),
        .Q(Q[7]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\right_out_reg[0]_0 ),
        .Q(\right_out_reg[3]_0 [0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\right_out_reg[1]_0 ),
        .Q(\right_out_reg[3]_0 [1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\right_out_reg[2]_1 ),
        .Q(\right_out_reg[3]_0 [2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\right_out_reg[3]_2 ),
        .Q(\right_out_reg[3]_0 [3]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "pe" *) 
module pe_0
   (CO,
    Q,
    \right_out_reg[2]_0 ,
    \right_out_reg[3]_0 ,
    \right_out_reg[0]_0 ,
    \bottom_out_reg[3]_0 ,
    \bottom_out_reg[2]_0 ,
    \bottom_out_reg[1]_0 ,
    \right_out_reg[2]_1 ,
    \bottom_out_reg[2]_1 ,
    \bottom_out_reg[1]_1 ,
    \bottom_out_reg[0]_0 ,
    DI,
    S,
    psum0_carry__0_i_4__0_0,
    psum0_carry__0_i_4__0_1,
    \psum_reg[7]_0 ,
    product__1_carry__0_i_5__1_0,
    product__1_carry__0_i_5__1_1,
    product__1_carry__0_i_5__1_2,
    product__1_carry_0,
    product__1_carry__0_i_5__3_0,
    product__1_carry__0_0,
    product__1_carry__0_1,
    SR,
    D,
    CLK,
    \bottom_out_reg[3]_1 );
  output [0:0]CO;
  output [7:0]Q;
  output [2:0]\right_out_reg[2]_0 ;
  output [2:0]\right_out_reg[3]_0 ;
  output [3:0]\right_out_reg[0]_0 ;
  output [3:0]\bottom_out_reg[3]_0 ;
  output \bottom_out_reg[2]_0 ;
  output [1:0]\bottom_out_reg[1]_0 ;
  output [2:0]\right_out_reg[2]_1 ;
  output [1:0]\bottom_out_reg[2]_1 ;
  output [0:0]\bottom_out_reg[1]_1 ;
  output [1:0]\bottom_out_reg[0]_0 ;
  input [2:0]DI;
  input [3:0]S;
  input [2:0]psum0_carry__0_i_4__0_0;
  input [2:0]psum0_carry__0_i_4__0_1;
  input [0:0]\psum_reg[7]_0 ;
  input product__1_carry__0_i_5__1_0;
  input product__1_carry__0_i_5__1_1;
  input product__1_carry__0_i_5__1_2;
  input product__1_carry_0;
  input [3:0]product__1_carry__0_i_5__3_0;
  input product__1_carry__0_0;
  input product__1_carry__0_1;
  input [0:0]SR;
  input [3:0]D;
  input CLK;
  input [3:0]\bottom_out_reg[3]_1 ;

  wire CLK;
  wire [0:0]CO;
  wire [3:0]D;
  wire [2:0]DI;
  wire [7:0]Q;
  wire [3:0]S;
  wire [0:0]SR;
  wire [1:0]\bottom_out_reg[0]_0 ;
  wire [1:0]\bottom_out_reg[1]_0 ;
  wire [0:0]\bottom_out_reg[1]_1 ;
  wire \bottom_out_reg[2]_0 ;
  wire [1:0]\bottom_out_reg[2]_1 ;
  wire [3:0]\bottom_out_reg[3]_0 ;
  wire [3:0]\bottom_out_reg[3]_1 ;
  wire product__1_carry_0;
  wire product__1_carry__0_0;
  wire product__1_carry__0_1;
  wire product__1_carry__0_i_10__1_n_0;
  wire product__1_carry__0_i_5__1_0;
  wire product__1_carry__0_i_5__1_1;
  wire product__1_carry__0_i_5__1_2;
  wire [3:0]product__1_carry__0_i_5__3_0;
  wire product__1_carry__0_i_7__1_n_0;
  wire product__1_carry__0_i_8__1_n_0;
  wire product__1_carry__0_i_8__3_n_0;
  wire product__1_carry__0_i_9__1_n_0;
  wire product__1_carry__0_i_9__3_n_0;
  wire product__1_carry__0_n_2;
  wire product__1_carry__0_n_3;
  wire product__1_carry__0_n_5;
  wire product__1_carry__0_n_6;
  wire product__1_carry__0_n_7;
  wire product__1_carry_i_8__1_n_0;
  wire product__1_carry_n_0;
  wire product__1_carry_n_1;
  wire product__1_carry_n_2;
  wire product__1_carry_n_3;
  wire product__1_carry_n_4;
  wire product__1_carry_n_5;
  wire product__1_carry_n_6;
  wire product__1_carry_n_7;
  wire [7:0]psum0__0;
  wire psum0_carry__0_i_2__0_n_0;
  wire psum0_carry__0_i_3__0_n_0;
  wire [2:0]psum0_carry__0_i_4__0_0;
  wire [2:0]psum0_carry__0_i_4__0_1;
  wire psum0_carry__0_i_4__0_n_0;
  wire psum0_carry__0_n_1;
  wire psum0_carry__0_n_2;
  wire psum0_carry__0_n_3;
  wire psum0_carry_i_1__0_n_0;
  wire psum0_carry_i_2__0_n_0;
  wire psum0_carry_i_3__0_n_0;
  wire psum0_carry_i_4__0_n_0;
  wire psum0_carry_n_0;
  wire psum0_carry_n_1;
  wire psum0_carry_n_2;
  wire psum0_carry_n_3;
  wire [0:0]\psum_reg[7]_0 ;
  wire [3:0]\right_out_reg[0]_0 ;
  wire [2:0]\right_out_reg[2]_0 ;
  wire [2:0]\right_out_reg[2]_1 ;
  wire [2:0]\right_out_reg[3]_0 ;
  wire \right_out_reg_n_0_[0] ;
  wire \right_out_reg_n_0_[1] ;
  wire \right_out_reg_n_0_[2] ;
  wire \right_out_reg_n_0_[3] ;
  wire [2:2]NLW_product__1_carry__0_CO_UNCONNECTED;
  wire [3:3]NLW_product__1_carry__0_O_UNCONNECTED;
  wire [3:3]NLW_psum0_carry__0_CO_UNCONNECTED;

  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[3]_1 [0]),
        .Q(\bottom_out_reg[3]_0 [0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[3]_1 [1]),
        .Q(\bottom_out_reg[3]_0 [1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[3]_1 [2]),
        .Q(\bottom_out_reg[3]_0 [2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[3]_1 [3]),
        .Q(\bottom_out_reg[3]_0 [3]),
        .R(SR));
  CARRY4 product__1_carry
       (.CI(1'b0),
        .CO({product__1_carry_n_0,product__1_carry_n_1,product__1_carry_n_2,product__1_carry_n_3}),
        .CYINIT(1'b0),
        .DI({DI,1'b0}),
        .O({product__1_carry_n_4,product__1_carry_n_5,product__1_carry_n_6,product__1_carry_n_7}),
        .S(S));
  CARRY4 product__1_carry__0
       (.CI(product__1_carry_n_0),
        .CO({CO,NLW_product__1_carry__0_CO_UNCONNECTED[2],product__1_carry__0_n_2,product__1_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,psum0_carry__0_i_4__0_0}),
        .O({NLW_product__1_carry__0_O_UNCONNECTED[3],product__1_carry__0_n_5,product__1_carry__0_n_6,product__1_carry__0_n_7}),
        .S({1'b1,psum0_carry__0_i_4__0_1}));
  LUT6 #(
    .INIT(64'hF880880080800000)) 
    product__1_carry__0_i_10__1
       (.I0(\right_out_reg_n_0_[2] ),
        .I1(product__1_carry__0_i_5__1_0),
        .I2(\right_out_reg_n_0_[1] ),
        .I3(product__1_carry__0_i_5__1_2),
        .I4(product__1_carry__0_i_5__1_1),
        .I5(\right_out_reg_n_0_[0] ),
        .O(product__1_carry__0_i_10__1_n_0));
  LUT6 #(
    .INIT(64'hFC88800080000000)) 
    product__1_carry__0_i_1__1
       (.I0(product__1_carry__0_i_5__1_0),
        .I1(\right_out_reg_n_0_[3] ),
        .I2(\right_out_reg_n_0_[1] ),
        .I3(product__1_carry__0_i_5__1_2),
        .I4(product__1_carry__0_i_5__1_1),
        .I5(\right_out_reg_n_0_[2] ),
        .O(\right_out_reg[3]_0 [2]));
  LUT6 #(
    .INIT(64'hFC88800080000000)) 
    product__1_carry__0_i_1__3
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__3_0[3]),
        .I2(product__1_carry__0_i_5__3_0[1]),
        .I3(\bottom_out_reg[3]_0 [3]),
        .I4(\bottom_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__3_0[2]),
        .O(\bottom_out_reg[1]_0 [1]));
  LUT3 #(
    .INIT(8'h80)) 
    product__1_carry__0_i_2__1
       (.I0(product__1_carry_0),
        .I1(product__1_carry__0_i_7__1_n_0),
        .I2(\right_out_reg_n_0_[3] ),
        .O(\right_out_reg[3]_0 [1]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    product__1_carry__0_i_3__1
       (.I0(\right_out_reg_n_0_[3] ),
        .I1(product__1_carry__0_i_5__1_0),
        .I2(product__1_carry_i_8__1_n_0),
        .I3(\right_out_reg_n_0_[0] ),
        .I4(product__1_carry_0),
        .I5(product__1_carry__0_i_8__1_n_0),
        .O(\right_out_reg[3]_0 [0]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    product__1_carry__0_i_3__3
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(\bottom_out_reg[3]_0 [1]),
        .I2(\bottom_out_reg[2]_0 ),
        .I3(product__1_carry__0_i_5__3_0[0]),
        .I4(product__1_carry__0_i_5__3_0[3]),
        .I5(product__1_carry__0_i_8__3_n_0),
        .O(\bottom_out_reg[1]_0 [0]));
  LUT6 #(
    .INIT(64'h1777808088000000)) 
    product__1_carry__0_i_4__1
       (.I0(\right_out_reg_n_0_[2] ),
        .I1(product__1_carry__0_i_5__1_1),
        .I2(\right_out_reg_n_0_[1] ),
        .I3(product__1_carry__0_i_5__1_0),
        .I4(\right_out_reg_n_0_[3] ),
        .I5(product__1_carry__0_i_5__1_2),
        .O(\right_out_reg[2]_1 [2]));
  LUT4 #(
    .INIT(16'h7F80)) 
    product__1_carry__0_i_5__1
       (.I0(\right_out_reg_n_0_[3] ),
        .I1(product__1_carry__0_i_7__1_n_0),
        .I2(product__1_carry_0),
        .I3(product__1_carry__0_i_9__1_n_0),
        .O(\right_out_reg[2]_1 [1]));
  LUT4 #(
    .INIT(16'h7F80)) 
    product__1_carry__0_i_5__3
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_1),
        .I2(product__1_carry__0_i_5__3_0[3]),
        .I3(product__1_carry__0_i_9__3_n_0),
        .O(\bottom_out_reg[0]_0 [1]));
  LUT2 #(
    .INIT(4'h6)) 
    product__1_carry__0_i_6__1
       (.I0(\right_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_10__1_n_0),
        .O(\right_out_reg[2]_1 [0]));
  LUT2 #(
    .INIT(4'h6)) 
    product__1_carry__0_i_6__3
       (.I0(\bottom_out_reg[1]_0 [0]),
        .I1(product__1_carry__0_0),
        .O(\bottom_out_reg[0]_0 [0]));
  LUT6 #(
    .INIT(64'h8000200000000000)) 
    product__1_carry__0_i_7__1
       (.I0(\right_out_reg_n_0_[0] ),
        .I1(product__1_carry__0_i_5__1_2),
        .I2(product__1_carry__0_i_5__1_1),
        .I3(\right_out_reg_n_0_[1] ),
        .I4(\right_out_reg_n_0_[2] ),
        .I5(product__1_carry__0_i_5__1_0),
        .O(product__1_carry__0_i_7__1_n_0));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry__0_i_8__1
       (.I0(product__1_carry__0_i_5__1_0),
        .I1(\right_out_reg_n_0_[3] ),
        .I2(product__1_carry__0_i_5__1_1),
        .I3(\right_out_reg_n_0_[2] ),
        .I4(product__1_carry__0_i_5__1_2),
        .I5(\right_out_reg_n_0_[1] ),
        .O(product__1_carry__0_i_8__1_n_0));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry__0_i_8__3
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__3_0[3]),
        .I2(\bottom_out_reg[3]_0 [2]),
        .I3(product__1_carry__0_i_5__3_0[2]),
        .I4(\bottom_out_reg[3]_0 [3]),
        .I5(product__1_carry__0_i_5__3_0[1]),
        .O(product__1_carry__0_i_8__3_n_0));
  LUT6 #(
    .INIT(64'hC4B470F04CCC8000)) 
    product__1_carry__0_i_9__1
       (.I0(product__1_carry__0_i_5__1_0),
        .I1(\right_out_reg_n_0_[3] ),
        .I2(product__1_carry__0_i_5__1_2),
        .I3(\right_out_reg_n_0_[1] ),
        .I4(product__1_carry__0_i_5__1_1),
        .I5(\right_out_reg_n_0_[2] ),
        .O(product__1_carry__0_i_9__1_n_0));
  LUT6 #(
    .INIT(64'hC4B470F04CCC8000)) 
    product__1_carry__0_i_9__3
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__3_0[3]),
        .I2(\bottom_out_reg[3]_0 [3]),
        .I3(product__1_carry__0_i_5__3_0[1]),
        .I4(\bottom_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__3_0[2]),
        .O(product__1_carry__0_i_9__3_n_0));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_1__1
       (.I0(\right_out_reg_n_0_[2] ),
        .I1(product__1_carry__0_i_5__1_0),
        .I2(product__1_carry__0_i_5__1_2),
        .I3(\right_out_reg_n_0_[0] ),
        .I4(product__1_carry__0_i_5__1_1),
        .I5(\right_out_reg_n_0_[1] ),
        .O(\right_out_reg[2]_0 [2]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_2__1
       (.I0(product__1_carry__0_i_5__1_0),
        .I1(\right_out_reg_n_0_[1] ),
        .I2(\right_out_reg_n_0_[0] ),
        .I3(product__1_carry__0_i_5__1_1),
        .O(\right_out_reg[2]_0 [1]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_2__3
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__3_0[1]),
        .I2(product__1_carry__0_i_5__3_0[0]),
        .I3(\bottom_out_reg[3]_0 [2]),
        .O(\bottom_out_reg[1]_1 ));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_3__1
       (.I0(\right_out_reg_n_0_[1] ),
        .I1(product__1_carry_0),
        .O(\right_out_reg[2]_0 [0]));
  LUT6 #(
    .INIT(64'h95556AAA6AAA6AAA)) 
    product__1_carry_i_4__1
       (.I0(\right_out_reg[2]_0 [2]),
        .I1(product__1_carry__0_i_5__1_0),
        .I2(product__1_carry_i_8__1_n_0),
        .I3(\right_out_reg_n_0_[0] ),
        .I4(\right_out_reg_n_0_[3] ),
        .I5(product__1_carry_0),
        .O(\right_out_reg[0]_0 [3]));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_5__1
       (.I0(product__1_carry__0_i_5__1_1),
        .I1(\right_out_reg_n_0_[0] ),
        .I2(\right_out_reg_n_0_[1] ),
        .I3(product__1_carry__0_i_5__1_0),
        .I4(product__1_carry_0),
        .I5(\right_out_reg_n_0_[2] ),
        .O(\right_out_reg[0]_0 [2]));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_5__3
       (.I0(\bottom_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__3_0[0]),
        .I2(product__1_carry__0_i_5__3_0[1]),
        .I3(\bottom_out_reg[3]_0 [1]),
        .I4(\bottom_out_reg[3]_0 [0]),
        .I5(product__1_carry__0_i_5__3_0[2]),
        .O(\bottom_out_reg[2]_1 [1]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_6__1
       (.I0(product__1_carry_0),
        .I1(\right_out_reg_n_0_[1] ),
        .I2(product__1_carry__0_i_5__1_0),
        .I3(\right_out_reg_n_0_[0] ),
        .O(\right_out_reg[0]_0 [1]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_6__3
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_5__3_0[1]),
        .I2(\bottom_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__3_0[0]),
        .O(\bottom_out_reg[2]_1 [0]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_7__1
       (.I0(\right_out_reg_n_0_[0] ),
        .I1(product__1_carry_0),
        .O(\right_out_reg[0]_0 [0]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_8__1
       (.I0(product__1_carry__0_i_5__1_1),
        .I1(\right_out_reg_n_0_[1] ),
        .O(product__1_carry_i_8__1_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_8__3
       (.I0(\bottom_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__3_0[1]),
        .O(\bottom_out_reg[2]_0 ));
  CARRY4 psum0_carry
       (.CI(1'b0),
        .CO({psum0_carry_n_0,psum0_carry_n_1,psum0_carry_n_2,psum0_carry_n_3}),
        .CYINIT(1'b0),
        .DI(Q[3:0]),
        .O(psum0__0[3:0]),
        .S({psum0_carry_i_1__0_n_0,psum0_carry_i_2__0_n_0,psum0_carry_i_3__0_n_0,psum0_carry_i_4__0_n_0}));
  CARRY4 psum0_carry__0
       (.CI(psum0_carry_n_0),
        .CO({NLW_psum0_carry__0_CO_UNCONNECTED[3],psum0_carry__0_n_1,psum0_carry__0_n_2,psum0_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,Q[6:4]}),
        .O(psum0__0[7:4]),
        .S({\psum_reg[7]_0 ,psum0_carry__0_i_2__0_n_0,psum0_carry__0_i_3__0_n_0,psum0_carry__0_i_4__0_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_2__0
       (.I0(Q[6]),
        .I1(product__1_carry__0_n_5),
        .O(psum0_carry__0_i_2__0_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_3__0
       (.I0(Q[5]),
        .I1(product__1_carry__0_n_6),
        .O(psum0_carry__0_i_3__0_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_4__0
       (.I0(Q[4]),
        .I1(product__1_carry__0_n_7),
        .O(psum0_carry__0_i_4__0_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_1__0
       (.I0(Q[3]),
        .I1(product__1_carry_n_4),
        .O(psum0_carry_i_1__0_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_2__0
       (.I0(Q[2]),
        .I1(product__1_carry_n_5),
        .O(psum0_carry_i_2__0_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_3__0
       (.I0(Q[1]),
        .I1(product__1_carry_n_6),
        .O(psum0_carry_i_3__0_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_4__0
       (.I0(Q[0]),
        .I1(product__1_carry_n_7),
        .O(psum0_carry_i_4__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__0[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__0[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__0[2]),
        .Q(Q[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__0[3]),
        .Q(Q[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__0[4]),
        .Q(Q[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__0[5]),
        .Q(Q[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__0[6]),
        .Q(Q[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__0[7]),
        .Q(Q[7]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\right_out_reg_n_0_[0] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\right_out_reg_n_0_[1] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\right_out_reg_n_0_[2] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(\right_out_reg_n_0_[3] ),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "pe" *) 
module pe_1
   (Q,
    \bottom_out_reg[3]_0 ,
    \bottom_out_reg[2]_0 ,
    DI,
    S,
    \bottom_out_reg[1]_0 ,
    \bottom_out_reg[0]_0 ,
    psum0_carry_i_4__1_0,
    psum0_carry_i_4__1_1,
    psum0_carry__0_i_4__1_0,
    psum0_carry__0_i_4__1_1,
    product__1_carry__0_i_5__4_0,
    product__1_carry__0_0,
    product__1_carry__0_1,
    SR,
    D,
    CLK);
  output [7:0]Q;
  output [3:0]\bottom_out_reg[3]_0 ;
  output \bottom_out_reg[2]_0 ;
  output [1:0]DI;
  output [1:0]S;
  output [0:0]\bottom_out_reg[1]_0 ;
  output [1:0]\bottom_out_reg[0]_0 ;
  input [2:0]psum0_carry_i_4__1_0;
  input [3:0]psum0_carry_i_4__1_1;
  input [2:0]psum0_carry__0_i_4__1_0;
  input [2:0]psum0_carry__0_i_4__1_1;
  input [3:0]product__1_carry__0_i_5__4_0;
  input product__1_carry__0_0;
  input product__1_carry__0_1;
  input [0:0]SR;
  input [3:0]D;
  input CLK;

  wire CLK;
  wire [3:0]D;
  wire [1:0]DI;
  wire [7:0]Q;
  wire [1:0]S;
  wire [0:0]SR;
  wire [1:0]\bottom_out_reg[0]_0 ;
  wire [0:0]\bottom_out_reg[1]_0 ;
  wire \bottom_out_reg[2]_0 ;
  wire [3:0]\bottom_out_reg[3]_0 ;
  wire product__1_carry__0_0;
  wire product__1_carry__0_1;
  wire [3:0]product__1_carry__0_i_5__4_0;
  wire product__1_carry__0_i_8__4_n_0;
  wire product__1_carry__0_i_9__4_n_0;
  wire product__1_carry__0_n_0;
  wire product__1_carry__0_n_2;
  wire product__1_carry__0_n_3;
  wire product__1_carry__0_n_5;
  wire product__1_carry__0_n_6;
  wire product__1_carry__0_n_7;
  wire product__1_carry_n_0;
  wire product__1_carry_n_1;
  wire product__1_carry_n_2;
  wire product__1_carry_n_3;
  wire product__1_carry_n_4;
  wire product__1_carry_n_5;
  wire product__1_carry_n_6;
  wire product__1_carry_n_7;
  wire [7:0]psum0__1;
  wire psum0_carry__0_i_1__1_n_0;
  wire psum0_carry__0_i_2__1_n_0;
  wire psum0_carry__0_i_3__1_n_0;
  wire [2:0]psum0_carry__0_i_4__1_0;
  wire [2:0]psum0_carry__0_i_4__1_1;
  wire psum0_carry__0_i_4__1_n_0;
  wire psum0_carry__0_n_1;
  wire psum0_carry__0_n_2;
  wire psum0_carry__0_n_3;
  wire psum0_carry_i_1__1_n_0;
  wire psum0_carry_i_2__1_n_0;
  wire psum0_carry_i_3__1_n_0;
  wire [2:0]psum0_carry_i_4__1_0;
  wire [3:0]psum0_carry_i_4__1_1;
  wire psum0_carry_i_4__1_n_0;
  wire psum0_carry_n_0;
  wire psum0_carry_n_1;
  wire psum0_carry_n_2;
  wire psum0_carry_n_3;
  wire [2:2]NLW_product__1_carry__0_CO_UNCONNECTED;
  wire [3:3]NLW_product__1_carry__0_O_UNCONNECTED;
  wire [3:3]NLW_psum0_carry__0_CO_UNCONNECTED;

  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\bottom_out_reg[3]_0 [0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\bottom_out_reg[3]_0 [1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\bottom_out_reg[3]_0 [2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(\bottom_out_reg[3]_0 [3]),
        .R(SR));
  CARRY4 product__1_carry
       (.CI(1'b0),
        .CO({product__1_carry_n_0,product__1_carry_n_1,product__1_carry_n_2,product__1_carry_n_3}),
        .CYINIT(1'b0),
        .DI({psum0_carry_i_4__1_0,1'b0}),
        .O({product__1_carry_n_4,product__1_carry_n_5,product__1_carry_n_6,product__1_carry_n_7}),
        .S(psum0_carry_i_4__1_1));
  CARRY4 product__1_carry__0
       (.CI(product__1_carry_n_0),
        .CO({product__1_carry__0_n_0,NLW_product__1_carry__0_CO_UNCONNECTED[2],product__1_carry__0_n_2,product__1_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,psum0_carry__0_i_4__1_0}),
        .O({NLW_product__1_carry__0_O_UNCONNECTED[3],product__1_carry__0_n_5,product__1_carry__0_n_6,product__1_carry__0_n_7}),
        .S({1'b1,psum0_carry__0_i_4__1_1}));
  LUT6 #(
    .INIT(64'hFC88800080000000)) 
    product__1_carry__0_i_1__4
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__4_0[3]),
        .I2(product__1_carry__0_i_5__4_0[1]),
        .I3(\bottom_out_reg[3]_0 [3]),
        .I4(\bottom_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__4_0[2]),
        .O(DI[1]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    product__1_carry__0_i_3__4
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(\bottom_out_reg[3]_0 [1]),
        .I2(\bottom_out_reg[2]_0 ),
        .I3(product__1_carry__0_i_5__4_0[0]),
        .I4(product__1_carry__0_i_5__4_0[3]),
        .I5(product__1_carry__0_i_8__4_n_0),
        .O(DI[0]));
  LUT4 #(
    .INIT(16'h7F80)) 
    product__1_carry__0_i_5__4
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_1),
        .I2(product__1_carry__0_i_5__4_0[3]),
        .I3(product__1_carry__0_i_9__4_n_0),
        .O(\bottom_out_reg[0]_0 [1]));
  LUT2 #(
    .INIT(4'h6)) 
    product__1_carry__0_i_6__4
       (.I0(DI[0]),
        .I1(product__1_carry__0_0),
        .O(\bottom_out_reg[0]_0 [0]));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry__0_i_8__4
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__4_0[3]),
        .I2(\bottom_out_reg[3]_0 [2]),
        .I3(product__1_carry__0_i_5__4_0[2]),
        .I4(\bottom_out_reg[3]_0 [3]),
        .I5(product__1_carry__0_i_5__4_0[1]),
        .O(product__1_carry__0_i_8__4_n_0));
  LUT6 #(
    .INIT(64'hC4B470F04CCC8000)) 
    product__1_carry__0_i_9__4
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__4_0[3]),
        .I2(\bottom_out_reg[3]_0 [3]),
        .I3(product__1_carry__0_i_5__4_0[1]),
        .I4(\bottom_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__4_0[2]),
        .O(product__1_carry__0_i_9__4_n_0));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_2__4
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__4_0[1]),
        .I2(product__1_carry__0_i_5__4_0[0]),
        .I3(\bottom_out_reg[3]_0 [2]),
        .O(\bottom_out_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_5__4
       (.I0(\bottom_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__4_0[0]),
        .I2(product__1_carry__0_i_5__4_0[1]),
        .I3(\bottom_out_reg[3]_0 [1]),
        .I4(\bottom_out_reg[3]_0 [0]),
        .I5(product__1_carry__0_i_5__4_0[2]),
        .O(S[1]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_6__4
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_5__4_0[1]),
        .I2(\bottom_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__4_0[0]),
        .O(S[0]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_8__4
       (.I0(\bottom_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__4_0[1]),
        .O(\bottom_out_reg[2]_0 ));
  CARRY4 psum0_carry
       (.CI(1'b0),
        .CO({psum0_carry_n_0,psum0_carry_n_1,psum0_carry_n_2,psum0_carry_n_3}),
        .CYINIT(1'b0),
        .DI(Q[3:0]),
        .O(psum0__1[3:0]),
        .S({psum0_carry_i_1__1_n_0,psum0_carry_i_2__1_n_0,psum0_carry_i_3__1_n_0,psum0_carry_i_4__1_n_0}));
  CARRY4 psum0_carry__0
       (.CI(psum0_carry_n_0),
        .CO({NLW_psum0_carry__0_CO_UNCONNECTED[3],psum0_carry__0_n_1,psum0_carry__0_n_2,psum0_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,Q[6:4]}),
        .O(psum0__1[7:4]),
        .S({psum0_carry__0_i_1__1_n_0,psum0_carry__0_i_2__1_n_0,psum0_carry__0_i_3__1_n_0,psum0_carry__0_i_4__1_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_1__1
       (.I0(Q[7]),
        .I1(product__1_carry__0_n_0),
        .O(psum0_carry__0_i_1__1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_2__1
       (.I0(Q[6]),
        .I1(product__1_carry__0_n_5),
        .O(psum0_carry__0_i_2__1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_3__1
       (.I0(Q[5]),
        .I1(product__1_carry__0_n_6),
        .O(psum0_carry__0_i_3__1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_4__1
       (.I0(Q[4]),
        .I1(product__1_carry__0_n_7),
        .O(psum0_carry__0_i_4__1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_1__1
       (.I0(Q[3]),
        .I1(product__1_carry_n_4),
        .O(psum0_carry_i_1__1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_2__1
       (.I0(Q[2]),
        .I1(product__1_carry_n_5),
        .O(psum0_carry_i_2__1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_3__1
       (.I0(Q[1]),
        .I1(product__1_carry_n_6),
        .O(psum0_carry_i_3__1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_4__1
       (.I0(Q[0]),
        .I1(product__1_carry_n_7),
        .O(psum0_carry_i_4__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__1[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__1[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__1[2]),
        .Q(Q[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__1[3]),
        .Q(Q[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__1[4]),
        .Q(Q[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__1[5]),
        .Q(Q[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__1[6]),
        .Q(Q[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__1[7]),
        .Q(Q[7]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "pe" *) 
module pe_2
   (Q,
    DI,
    \right_out_reg[3]_0 ,
    \right_out_reg[2]_0 ,
    \right_out_reg[3]_1 ,
    \right_out_reg[0]_0 ,
    S,
    \bottom_out_reg[1]_0 ,
    \bottom_out_reg[1]_1 ,
    \bottom_out_reg[1]_2 ,
    \right_out_reg[2]_1 ,
    \bottom_out_reg[2]_0 ,
    psum0_carry_i_4__2_0,
    psum0_carry_i_4__2_1,
    psum0_carry__0_i_4__2_0,
    psum0_carry__0_i_4__2_1,
    product__1_carry__0_i_5__3,
    product__1_carry__0_0,
    product__1_carry__0_i_5__5_0,
    product__1_carry_0,
    product__1_carry_1,
    product__1_carry_2,
    SR,
    D,
    CLK,
    \bottom_out_reg[3]_0 );
  output [7:0]Q;
  output [1:0]DI;
  output [3:0]\right_out_reg[3]_0 ;
  output \right_out_reg[2]_0 ;
  output [0:0]\right_out_reg[3]_1 ;
  output \right_out_reg[0]_0 ;
  output [1:0]S;
  output [2:0]\bottom_out_reg[1]_0 ;
  output [2:0]\bottom_out_reg[1]_1 ;
  output [3:0]\bottom_out_reg[1]_2 ;
  output [0:0]\right_out_reg[2]_1 ;
  output [2:0]\bottom_out_reg[2]_0 ;
  input [2:0]psum0_carry_i_4__2_0;
  input [3:0]psum0_carry_i_4__2_1;
  input [2:0]psum0_carry__0_i_4__2_0;
  input [2:0]psum0_carry__0_i_4__2_1;
  input [3:0]product__1_carry__0_i_5__3;
  input product__1_carry__0_0;
  input product__1_carry__0_i_5__5_0;
  input product__1_carry_0;
  input product__1_carry_1;
  input product__1_carry_2;
  input [0:0]SR;
  input [3:0]D;
  input CLK;
  input [3:0]\bottom_out_reg[3]_0 ;

  wire CLK;
  wire [3:0]D;
  wire [1:0]DI;
  wire [7:0]Q;
  wire [1:0]S;
  wire [0:0]SR;
  wire [2:0]\bottom_out_reg[1]_0 ;
  wire [2:0]\bottom_out_reg[1]_1 ;
  wire [3:0]\bottom_out_reg[1]_2 ;
  wire [2:0]\bottom_out_reg[2]_0 ;
  wire [3:0]\bottom_out_reg[3]_0 ;
  wire \bottom_out_reg_n_0_[0] ;
  wire \bottom_out_reg_n_0_[1] ;
  wire \bottom_out_reg_n_0_[2] ;
  wire \bottom_out_reg_n_0_[3] ;
  wire product__1_carry_0;
  wire product__1_carry_1;
  wire product__1_carry_2;
  wire product__1_carry__0_0;
  wire product__1_carry__0_i_10__5_n_0;
  wire [3:0]product__1_carry__0_i_5__3;
  wire product__1_carry__0_i_5__5_0;
  wire product__1_carry__0_i_7__5_n_0;
  wire product__1_carry__0_i_8__5_n_0;
  wire product__1_carry__0_i_9__5_n_0;
  wire product__1_carry__0_n_0;
  wire product__1_carry__0_n_2;
  wire product__1_carry__0_n_3;
  wire product__1_carry__0_n_5;
  wire product__1_carry__0_n_6;
  wire product__1_carry__0_n_7;
  wire product__1_carry_i_8__5_n_0;
  wire product__1_carry_n_0;
  wire product__1_carry_n_1;
  wire product__1_carry_n_2;
  wire product__1_carry_n_3;
  wire product__1_carry_n_4;
  wire product__1_carry_n_5;
  wire product__1_carry_n_6;
  wire product__1_carry_n_7;
  wire [7:0]psum0__2;
  wire psum0_carry__0_i_1__2_n_0;
  wire psum0_carry__0_i_2__2_n_0;
  wire psum0_carry__0_i_3__2_n_0;
  wire [2:0]psum0_carry__0_i_4__2_0;
  wire [2:0]psum0_carry__0_i_4__2_1;
  wire psum0_carry__0_i_4__2_n_0;
  wire psum0_carry__0_n_1;
  wire psum0_carry__0_n_2;
  wire psum0_carry__0_n_3;
  wire psum0_carry_i_1__2_n_0;
  wire psum0_carry_i_2__2_n_0;
  wire psum0_carry_i_3__2_n_0;
  wire [2:0]psum0_carry_i_4__2_0;
  wire [3:0]psum0_carry_i_4__2_1;
  wire psum0_carry_i_4__2_n_0;
  wire psum0_carry_n_0;
  wire psum0_carry_n_1;
  wire psum0_carry_n_2;
  wire psum0_carry_n_3;
  wire \right_out_reg[0]_0 ;
  wire \right_out_reg[2]_0 ;
  wire [0:0]\right_out_reg[2]_1 ;
  wire [3:0]\right_out_reg[3]_0 ;
  wire [0:0]\right_out_reg[3]_1 ;
  wire [2:2]NLW_product__1_carry__0_CO_UNCONNECTED;
  wire [3:3]NLW_product__1_carry__0_O_UNCONNECTED;
  wire [3:3]NLW_psum0_carry__0_CO_UNCONNECTED;

  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[3]_0 [0]),
        .Q(\bottom_out_reg_n_0_[0] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[3]_0 [1]),
        .Q(\bottom_out_reg_n_0_[1] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[3]_0 [2]),
        .Q(\bottom_out_reg_n_0_[2] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[3]_0 [3]),
        .Q(\bottom_out_reg_n_0_[3] ),
        .R(SR));
  CARRY4 product__1_carry
       (.CI(1'b0),
        .CO({product__1_carry_n_0,product__1_carry_n_1,product__1_carry_n_2,product__1_carry_n_3}),
        .CYINIT(1'b0),
        .DI({psum0_carry_i_4__2_0,1'b0}),
        .O({product__1_carry_n_4,product__1_carry_n_5,product__1_carry_n_6,product__1_carry_n_7}),
        .S(psum0_carry_i_4__2_1));
  CARRY4 product__1_carry__0
       (.CI(product__1_carry_n_0),
        .CO({product__1_carry__0_n_0,NLW_product__1_carry__0_CO_UNCONNECTED[2],product__1_carry__0_n_2,product__1_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,psum0_carry__0_i_4__2_0}),
        .O({NLW_product__1_carry__0_O_UNCONNECTED[3],product__1_carry__0_n_5,product__1_carry__0_n_6,product__1_carry__0_n_7}),
        .S({1'b1,psum0_carry__0_i_4__2_1}));
  LUT6 #(
    .INIT(64'hF880880080800000)) 
    product__1_carry__0_i_10__3
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__3[1]),
        .I2(\right_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__3[3]),
        .I4(product__1_carry__0_i_5__3[2]),
        .I5(\right_out_reg[3]_0 [0]),
        .O(\right_out_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hF880880080800000)) 
    product__1_carry__0_i_10__5
       (.I0(product__1_carry__0_i_5__5_0),
        .I1(\bottom_out_reg_n_0_[1] ),
        .I2(product__1_carry_0),
        .I3(\bottom_out_reg_n_0_[3] ),
        .I4(\bottom_out_reg_n_0_[2] ),
        .I5(product__1_carry_1),
        .O(product__1_carry__0_i_10__5_n_0));
  LUT6 #(
    .INIT(64'hFC88800080000000)) 
    product__1_carry__0_i_1__5
       (.I0(\bottom_out_reg_n_0_[1] ),
        .I1(product__1_carry__0_0),
        .I2(product__1_carry_0),
        .I3(\bottom_out_reg_n_0_[3] ),
        .I4(\bottom_out_reg_n_0_[2] ),
        .I5(product__1_carry__0_i_5__5_0),
        .O(\bottom_out_reg[1]_1 [2]));
  LUT3 #(
    .INIT(8'h80)) 
    product__1_carry__0_i_2__3
       (.I0(\right_out_reg[3]_0 [3]),
        .I1(\right_out_reg[0]_0 ),
        .I2(product__1_carry__0_i_5__3[0]),
        .O(\right_out_reg[3]_1 ));
  LUT3 #(
    .INIT(8'h80)) 
    product__1_carry__0_i_2__5
       (.I0(product__1_carry__0_0),
        .I1(product__1_carry__0_i_7__5_n_0),
        .I2(\bottom_out_reg_n_0_[0] ),
        .O(\bottom_out_reg[1]_1 [1]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    product__1_carry__0_i_3__5
       (.I0(\bottom_out_reg_n_0_[0] ),
        .I1(\bottom_out_reg_n_0_[1] ),
        .I2(product__1_carry_i_8__5_n_0),
        .I3(product__1_carry_1),
        .I4(product__1_carry__0_0),
        .I5(product__1_carry__0_i_8__5_n_0),
        .O(\bottom_out_reg[1]_1 [0]));
  LUT6 #(
    .INIT(64'h1777808088000000)) 
    product__1_carry__0_i_4__3
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__3[2]),
        .I2(\right_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__3[1]),
        .I4(\right_out_reg[3]_0 [3]),
        .I5(product__1_carry__0_i_5__3[3]),
        .O(\right_out_reg[2]_1 ));
  LUT6 #(
    .INIT(64'h1777808088000000)) 
    product__1_carry__0_i_4__5
       (.I0(product__1_carry__0_i_5__5_0),
        .I1(\bottom_out_reg_n_0_[2] ),
        .I2(product__1_carry_0),
        .I3(\bottom_out_reg_n_0_[1] ),
        .I4(product__1_carry__0_0),
        .I5(\bottom_out_reg_n_0_[3] ),
        .O(\bottom_out_reg[2]_0 [2]));
  LUT4 #(
    .INIT(16'h7F80)) 
    product__1_carry__0_i_5__5
       (.I0(\bottom_out_reg_n_0_[0] ),
        .I1(product__1_carry__0_i_7__5_n_0),
        .I2(product__1_carry__0_0),
        .I3(product__1_carry__0_i_9__5_n_0),
        .O(\bottom_out_reg[2]_0 [1]));
  LUT2 #(
    .INIT(4'h6)) 
    product__1_carry__0_i_6__5
       (.I0(\bottom_out_reg[1]_1 [0]),
        .I1(product__1_carry__0_i_10__5_n_0),
        .O(\bottom_out_reg[2]_0 [0]));
  LUT6 #(
    .INIT(64'h8000200000000000)) 
    product__1_carry__0_i_7__3
       (.I0(\right_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_5__3[3]),
        .I2(product__1_carry__0_i_5__3[2]),
        .I3(\right_out_reg[3]_0 [1]),
        .I4(\right_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__3[1]),
        .O(\right_out_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h8000200000000000)) 
    product__1_carry__0_i_7__5
       (.I0(product__1_carry_1),
        .I1(\bottom_out_reg_n_0_[3] ),
        .I2(\bottom_out_reg_n_0_[2] ),
        .I3(product__1_carry_0),
        .I4(product__1_carry__0_i_5__5_0),
        .I5(\bottom_out_reg_n_0_[1] ),
        .O(product__1_carry__0_i_7__5_n_0));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry__0_i_8__5
       (.I0(\bottom_out_reg_n_0_[1] ),
        .I1(product__1_carry__0_0),
        .I2(\bottom_out_reg_n_0_[2] ),
        .I3(product__1_carry__0_i_5__5_0),
        .I4(\bottom_out_reg_n_0_[3] ),
        .I5(product__1_carry_0),
        .O(product__1_carry__0_i_8__5_n_0));
  LUT6 #(
    .INIT(64'hC4B470F04CCC8000)) 
    product__1_carry__0_i_9__5
       (.I0(\bottom_out_reg_n_0_[1] ),
        .I1(product__1_carry__0_0),
        .I2(\bottom_out_reg_n_0_[3] ),
        .I3(product__1_carry_0),
        .I4(\bottom_out_reg_n_0_[2] ),
        .I5(product__1_carry__0_i_5__5_0),
        .O(product__1_carry__0_i_9__5_n_0));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_1__3
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__3[1]),
        .I2(product__1_carry__0_i_5__3[3]),
        .I3(\right_out_reg[3]_0 [0]),
        .I4(product__1_carry__0_i_5__3[2]),
        .I5(\right_out_reg[3]_0 [1]),
        .O(DI[1]));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_1__5
       (.I0(product__1_carry__0_i_5__5_0),
        .I1(\bottom_out_reg_n_0_[1] ),
        .I2(\bottom_out_reg_n_0_[3] ),
        .I3(product__1_carry_1),
        .I4(\bottom_out_reg_n_0_[2] ),
        .I5(product__1_carry_0),
        .O(\bottom_out_reg[1]_0 [2]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_2__5
       (.I0(\bottom_out_reg_n_0_[1] ),
        .I1(product__1_carry_0),
        .I2(product__1_carry_1),
        .I3(\bottom_out_reg_n_0_[2] ),
        .O(\bottom_out_reg[1]_0 [1]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_3__3
       (.I0(\right_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__3[0]),
        .O(DI[0]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_3__5
       (.I0(product__1_carry_0),
        .I1(\bottom_out_reg_n_0_[0] ),
        .O(\bottom_out_reg[1]_0 [0]));
  LUT6 #(
    .INIT(64'h95556AAA6AAA6AAA)) 
    product__1_carry_i_4__3
       (.I0(DI[1]),
        .I1(product__1_carry__0_i_5__3[1]),
        .I2(product__1_carry_2),
        .I3(\right_out_reg[3]_0 [0]),
        .I4(product__1_carry__0_i_5__3[0]),
        .I5(\right_out_reg[3]_0 [3]),
        .O(S[1]));
  LUT6 #(
    .INIT(64'h95556AAA6AAA6AAA)) 
    product__1_carry_i_4__5
       (.I0(\bottom_out_reg[1]_0 [2]),
        .I1(\bottom_out_reg_n_0_[1] ),
        .I2(product__1_carry_i_8__5_n_0),
        .I3(product__1_carry_1),
        .I4(\bottom_out_reg_n_0_[0] ),
        .I5(product__1_carry__0_0),
        .O(\bottom_out_reg[1]_2 [3]));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_5__5
       (.I0(\bottom_out_reg_n_0_[2] ),
        .I1(product__1_carry_1),
        .I2(product__1_carry_0),
        .I3(\bottom_out_reg_n_0_[1] ),
        .I4(\bottom_out_reg_n_0_[0] ),
        .I5(product__1_carry__0_i_5__5_0),
        .O(\bottom_out_reg[1]_2 [2]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_6__5
       (.I0(\bottom_out_reg_n_0_[0] ),
        .I1(product__1_carry_0),
        .I2(\bottom_out_reg_n_0_[1] ),
        .I3(product__1_carry_1),
        .O(\bottom_out_reg[1]_2 [1]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_7__3
       (.I0(\right_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_5__3[0]),
        .O(S[0]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_7__5
       (.I0(product__1_carry_1),
        .I1(\bottom_out_reg_n_0_[0] ),
        .O(\bottom_out_reg[1]_2 [0]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_8__5
       (.I0(\bottom_out_reg_n_0_[2] ),
        .I1(product__1_carry_0),
        .O(product__1_carry_i_8__5_n_0));
  CARRY4 psum0_carry
       (.CI(1'b0),
        .CO({psum0_carry_n_0,psum0_carry_n_1,psum0_carry_n_2,psum0_carry_n_3}),
        .CYINIT(1'b0),
        .DI(Q[3:0]),
        .O(psum0__2[3:0]),
        .S({psum0_carry_i_1__2_n_0,psum0_carry_i_2__2_n_0,psum0_carry_i_3__2_n_0,psum0_carry_i_4__2_n_0}));
  CARRY4 psum0_carry__0
       (.CI(psum0_carry_n_0),
        .CO({NLW_psum0_carry__0_CO_UNCONNECTED[3],psum0_carry__0_n_1,psum0_carry__0_n_2,psum0_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,Q[6:4]}),
        .O(psum0__2[7:4]),
        .S({psum0_carry__0_i_1__2_n_0,psum0_carry__0_i_2__2_n_0,psum0_carry__0_i_3__2_n_0,psum0_carry__0_i_4__2_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_1__2
       (.I0(Q[7]),
        .I1(product__1_carry__0_n_0),
        .O(psum0_carry__0_i_1__2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_2__2
       (.I0(Q[6]),
        .I1(product__1_carry__0_n_5),
        .O(psum0_carry__0_i_2__2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_3__2
       (.I0(Q[5]),
        .I1(product__1_carry__0_n_6),
        .O(psum0_carry__0_i_3__2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_4__2
       (.I0(Q[4]),
        .I1(product__1_carry__0_n_7),
        .O(psum0_carry__0_i_4__2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_1__2
       (.I0(Q[3]),
        .I1(product__1_carry_n_4),
        .O(psum0_carry_i_1__2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_2__2
       (.I0(Q[2]),
        .I1(product__1_carry_n_5),
        .O(psum0_carry_i_2__2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_3__2
       (.I0(Q[1]),
        .I1(product__1_carry_n_6),
        .O(psum0_carry_i_3__2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_4__2
       (.I0(Q[0]),
        .I1(product__1_carry_n_7),
        .O(psum0_carry_i_4__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__2[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__2[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__2[2]),
        .Q(Q[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__2[3]),
        .Q(Q[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__2[4]),
        .Q(Q[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__2[5]),
        .Q(Q[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__2[6]),
        .Q(Q[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__2[7]),
        .Q(Q[7]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\right_out_reg[3]_0 [0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\right_out_reg[3]_0 [1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\right_out_reg[3]_0 [2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(\right_out_reg[3]_0 [3]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "pe" *) 
module pe_3
   (Q,
    \right_out_reg[2]_0 ,
    \right_out_reg[3]_0 ,
    \right_out_reg[2]_1 ,
    \right_out_reg[3]_1 ,
    \right_out_reg[0]_0 ,
    \bottom_out_reg[1]_0 ,
    \bottom_out_reg[3]_0 ,
    \bottom_out_reg[2]_0 ,
    \bottom_out_reg[1]_1 ,
    \right_out_reg[2]_2 ,
    \bottom_out_reg[2]_1 ,
    \bottom_out_reg[1]_2 ,
    \bottom_out_reg[0]_0 ,
    DI,
    S,
    psum0_carry__0_i_4__3_0,
    psum0_carry__0_i_4__3_1,
    product__1_carry__0_i_5__4,
    product__1_carry__0_i_5__6_0,
    product__1_carry_0,
    product__1_carry__0_0,
    product__1_carry__0_1,
    SR,
    D,
    CLK,
    \bottom_out_reg[3]_1 );
  output [7:0]Q;
  output [1:0]\right_out_reg[2]_0 ;
  output [3:0]\right_out_reg[3]_0 ;
  output \right_out_reg[2]_1 ;
  output [0:0]\right_out_reg[3]_1 ;
  output \right_out_reg[0]_0 ;
  output [1:0]\bottom_out_reg[1]_0 ;
  output [3:0]\bottom_out_reg[3]_0 ;
  output \bottom_out_reg[2]_0 ;
  output [1:0]\bottom_out_reg[1]_1 ;
  output [0:0]\right_out_reg[2]_2 ;
  output [1:0]\bottom_out_reg[2]_1 ;
  output [0:0]\bottom_out_reg[1]_2 ;
  output [1:0]\bottom_out_reg[0]_0 ;
  input [2:0]DI;
  input [3:0]S;
  input [2:0]psum0_carry__0_i_4__3_0;
  input [2:0]psum0_carry__0_i_4__3_1;
  input [3:0]product__1_carry__0_i_5__4;
  input [3:0]product__1_carry__0_i_5__6_0;
  input product__1_carry_0;
  input product__1_carry__0_0;
  input product__1_carry__0_1;
  input [0:0]SR;
  input [3:0]D;
  input CLK;
  input [3:0]\bottom_out_reg[3]_1 ;

  wire CLK;
  wire [3:0]D;
  wire [2:0]DI;
  wire [7:0]Q;
  wire [3:0]S;
  wire [0:0]SR;
  wire [1:0]\bottom_out_reg[0]_0 ;
  wire [1:0]\bottom_out_reg[1]_0 ;
  wire [1:0]\bottom_out_reg[1]_1 ;
  wire [0:0]\bottom_out_reg[1]_2 ;
  wire \bottom_out_reg[2]_0 ;
  wire [1:0]\bottom_out_reg[2]_1 ;
  wire [3:0]\bottom_out_reg[3]_0 ;
  wire [3:0]\bottom_out_reg[3]_1 ;
  wire product__1_carry_0;
  wire product__1_carry__0_0;
  wire product__1_carry__0_1;
  wire [3:0]product__1_carry__0_i_5__4;
  wire [3:0]product__1_carry__0_i_5__6_0;
  wire product__1_carry__0_i_8__6_n_0;
  wire product__1_carry__0_i_9__6_n_0;
  wire product__1_carry__0_n_0;
  wire product__1_carry__0_n_2;
  wire product__1_carry__0_n_3;
  wire product__1_carry__0_n_5;
  wire product__1_carry__0_n_6;
  wire product__1_carry__0_n_7;
  wire product__1_carry_n_0;
  wire product__1_carry_n_1;
  wire product__1_carry_n_2;
  wire product__1_carry_n_3;
  wire product__1_carry_n_4;
  wire product__1_carry_n_5;
  wire product__1_carry_n_6;
  wire product__1_carry_n_7;
  wire [7:0]psum0__3;
  wire psum0_carry__0_i_1__3_n_0;
  wire psum0_carry__0_i_2__3_n_0;
  wire psum0_carry__0_i_3__3_n_0;
  wire [2:0]psum0_carry__0_i_4__3_0;
  wire [2:0]psum0_carry__0_i_4__3_1;
  wire psum0_carry__0_i_4__3_n_0;
  wire psum0_carry__0_n_1;
  wire psum0_carry__0_n_2;
  wire psum0_carry__0_n_3;
  wire psum0_carry_i_1__3_n_0;
  wire psum0_carry_i_2__3_n_0;
  wire psum0_carry_i_3__3_n_0;
  wire psum0_carry_i_4__3_n_0;
  wire psum0_carry_n_0;
  wire psum0_carry_n_1;
  wire psum0_carry_n_2;
  wire psum0_carry_n_3;
  wire \right_out_reg[0]_0 ;
  wire [1:0]\right_out_reg[2]_0 ;
  wire \right_out_reg[2]_1 ;
  wire [0:0]\right_out_reg[2]_2 ;
  wire [3:0]\right_out_reg[3]_0 ;
  wire [0:0]\right_out_reg[3]_1 ;
  wire [2:2]NLW_product__1_carry__0_CO_UNCONNECTED;
  wire [3:3]NLW_product__1_carry__0_O_UNCONNECTED;
  wire [3:3]NLW_psum0_carry__0_CO_UNCONNECTED;

  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[3]_1 [0]),
        .Q(\bottom_out_reg[3]_0 [0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[3]_1 [1]),
        .Q(\bottom_out_reg[3]_0 [1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[3]_1 [2]),
        .Q(\bottom_out_reg[3]_0 [2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\bottom_out_reg[3]_1 [3]),
        .Q(\bottom_out_reg[3]_0 [3]),
        .R(SR));
  CARRY4 product__1_carry
       (.CI(1'b0),
        .CO({product__1_carry_n_0,product__1_carry_n_1,product__1_carry_n_2,product__1_carry_n_3}),
        .CYINIT(1'b0),
        .DI({DI,1'b0}),
        .O({product__1_carry_n_4,product__1_carry_n_5,product__1_carry_n_6,product__1_carry_n_7}),
        .S(S));
  CARRY4 product__1_carry__0
       (.CI(product__1_carry_n_0),
        .CO({product__1_carry__0_n_0,NLW_product__1_carry__0_CO_UNCONNECTED[2],product__1_carry__0_n_2,product__1_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,psum0_carry__0_i_4__3_0}),
        .O({NLW_product__1_carry__0_O_UNCONNECTED[3],product__1_carry__0_n_5,product__1_carry__0_n_6,product__1_carry__0_n_7}),
        .S({1'b1,psum0_carry__0_i_4__3_1}));
  LUT6 #(
    .INIT(64'hF880880080800000)) 
    product__1_carry__0_i_10__4
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__4[1]),
        .I2(\right_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__4[3]),
        .I4(product__1_carry__0_i_5__4[2]),
        .I5(\right_out_reg[3]_0 [0]),
        .O(\right_out_reg[2]_1 ));
  LUT6 #(
    .INIT(64'hFC88800080000000)) 
    product__1_carry__0_i_1__6
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__6_0[3]),
        .I2(product__1_carry__0_i_5__6_0[1]),
        .I3(\bottom_out_reg[3]_0 [3]),
        .I4(\bottom_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__6_0[2]),
        .O(\bottom_out_reg[1]_1 [1]));
  LUT3 #(
    .INIT(8'h80)) 
    product__1_carry__0_i_2__4
       (.I0(\right_out_reg[3]_0 [3]),
        .I1(\right_out_reg[0]_0 ),
        .I2(product__1_carry__0_i_5__4[0]),
        .O(\right_out_reg[3]_1 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    product__1_carry__0_i_3__6
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(\bottom_out_reg[3]_0 [1]),
        .I2(\bottom_out_reg[2]_0 ),
        .I3(product__1_carry__0_i_5__6_0[0]),
        .I4(product__1_carry__0_i_5__6_0[3]),
        .I5(product__1_carry__0_i_8__6_n_0),
        .O(\bottom_out_reg[1]_1 [0]));
  LUT6 #(
    .INIT(64'h1777808088000000)) 
    product__1_carry__0_i_4__4
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__4[2]),
        .I2(\right_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__4[1]),
        .I4(\right_out_reg[3]_0 [3]),
        .I5(product__1_carry__0_i_5__4[3]),
        .O(\right_out_reg[2]_2 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    product__1_carry__0_i_5__6
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_1),
        .I2(product__1_carry__0_i_5__6_0[3]),
        .I3(product__1_carry__0_i_9__6_n_0),
        .O(\bottom_out_reg[0]_0 [1]));
  LUT2 #(
    .INIT(4'h6)) 
    product__1_carry__0_i_6__6
       (.I0(\bottom_out_reg[1]_1 [0]),
        .I1(product__1_carry__0_0),
        .O(\bottom_out_reg[0]_0 [0]));
  LUT6 #(
    .INIT(64'h8000200000000000)) 
    product__1_carry__0_i_7__4
       (.I0(\right_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_5__4[3]),
        .I2(product__1_carry__0_i_5__4[2]),
        .I3(\right_out_reg[3]_0 [1]),
        .I4(\right_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__4[1]),
        .O(\right_out_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry__0_i_8__6
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__6_0[3]),
        .I2(\bottom_out_reg[3]_0 [2]),
        .I3(product__1_carry__0_i_5__6_0[2]),
        .I4(\bottom_out_reg[3]_0 [3]),
        .I5(product__1_carry__0_i_5__6_0[1]),
        .O(product__1_carry__0_i_8__6_n_0));
  LUT6 #(
    .INIT(64'hC4B470F04CCC8000)) 
    product__1_carry__0_i_9__6
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__6_0[3]),
        .I2(\bottom_out_reg[3]_0 [3]),
        .I3(product__1_carry__0_i_5__6_0[1]),
        .I4(\bottom_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__6_0[2]),
        .O(product__1_carry__0_i_9__6_n_0));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_1__4
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__4[1]),
        .I2(product__1_carry__0_i_5__4[3]),
        .I3(\right_out_reg[3]_0 [0]),
        .I4(product__1_carry__0_i_5__4[2]),
        .I5(\right_out_reg[3]_0 [1]),
        .O(\right_out_reg[2]_0 [1]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_2__6
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__6_0[1]),
        .I2(product__1_carry__0_i_5__6_0[0]),
        .I3(\bottom_out_reg[3]_0 [2]),
        .O(\bottom_out_reg[1]_2 ));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_3__4
       (.I0(\right_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__4[0]),
        .O(\right_out_reg[2]_0 [0]));
  LUT6 #(
    .INIT(64'h95556AAA6AAA6AAA)) 
    product__1_carry_i_4__4
       (.I0(\right_out_reg[2]_0 [1]),
        .I1(product__1_carry__0_i_5__4[1]),
        .I2(product__1_carry_0),
        .I3(\right_out_reg[3]_0 [0]),
        .I4(product__1_carry__0_i_5__4[0]),
        .I5(\right_out_reg[3]_0 [3]),
        .O(\bottom_out_reg[1]_0 [1]));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_5__6
       (.I0(\bottom_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__6_0[0]),
        .I2(product__1_carry__0_i_5__6_0[1]),
        .I3(\bottom_out_reg[3]_0 [1]),
        .I4(\bottom_out_reg[3]_0 [0]),
        .I5(product__1_carry__0_i_5__6_0[2]),
        .O(\bottom_out_reg[2]_1 [1]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_6__6
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_5__6_0[1]),
        .I2(\bottom_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__6_0[0]),
        .O(\bottom_out_reg[2]_1 [0]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_7__4
       (.I0(\right_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_5__4[0]),
        .O(\bottom_out_reg[1]_0 [0]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_8__6
       (.I0(\bottom_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__6_0[1]),
        .O(\bottom_out_reg[2]_0 ));
  CARRY4 psum0_carry
       (.CI(1'b0),
        .CO({psum0_carry_n_0,psum0_carry_n_1,psum0_carry_n_2,psum0_carry_n_3}),
        .CYINIT(1'b0),
        .DI(Q[3:0]),
        .O(psum0__3[3:0]),
        .S({psum0_carry_i_1__3_n_0,psum0_carry_i_2__3_n_0,psum0_carry_i_3__3_n_0,psum0_carry_i_4__3_n_0}));
  CARRY4 psum0_carry__0
       (.CI(psum0_carry_n_0),
        .CO({NLW_psum0_carry__0_CO_UNCONNECTED[3],psum0_carry__0_n_1,psum0_carry__0_n_2,psum0_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,Q[6:4]}),
        .O(psum0__3[7:4]),
        .S({psum0_carry__0_i_1__3_n_0,psum0_carry__0_i_2__3_n_0,psum0_carry__0_i_3__3_n_0,psum0_carry__0_i_4__3_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_1__3
       (.I0(Q[7]),
        .I1(product__1_carry__0_n_0),
        .O(psum0_carry__0_i_1__3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_2__3
       (.I0(Q[6]),
        .I1(product__1_carry__0_n_5),
        .O(psum0_carry__0_i_2__3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_3__3
       (.I0(Q[5]),
        .I1(product__1_carry__0_n_6),
        .O(psum0_carry__0_i_3__3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_4__3
       (.I0(Q[4]),
        .I1(product__1_carry__0_n_7),
        .O(psum0_carry__0_i_4__3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_1__3
       (.I0(Q[3]),
        .I1(product__1_carry_n_4),
        .O(psum0_carry_i_1__3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_2__3
       (.I0(Q[2]),
        .I1(product__1_carry_n_5),
        .O(psum0_carry_i_2__3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_3__3
       (.I0(Q[1]),
        .I1(product__1_carry_n_6),
        .O(psum0_carry_i_3__3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_4__3
       (.I0(Q[0]),
        .I1(product__1_carry_n_7),
        .O(psum0_carry_i_4__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__3[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__3[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__3[2]),
        .Q(Q[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__3[3]),
        .Q(Q[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__3[4]),
        .Q(Q[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__3[5]),
        .Q(Q[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__3[6]),
        .Q(Q[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__3[7]),
        .Q(Q[7]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\right_out_reg[3]_0 [0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\right_out_reg[3]_0 [1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\right_out_reg[3]_0 [2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(\right_out_reg[3]_0 [3]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "pe" *) 
module pe_4
   (Q,
    \bottom_out_reg[3]_0 ,
    \bottom_out_reg[2]_0 ,
    \bottom_out_reg[1]_0 ,
    \bottom_out_reg[2]_1 ,
    \bottom_out_reg[1]_1 ,
    \bottom_out_reg[0]_0 ,
    DI,
    S,
    psum0_carry__0_i_4__4_0,
    psum0_carry__0_i_4__4_1,
    product__1_carry__0_i_5__7_0,
    product__1_carry__0_0,
    product__1_carry__0_1,
    SR,
    D,
    CLK);
  output [7:0]Q;
  output [3:0]\bottom_out_reg[3]_0 ;
  output \bottom_out_reg[2]_0 ;
  output [1:0]\bottom_out_reg[1]_0 ;
  output [1:0]\bottom_out_reg[2]_1 ;
  output [0:0]\bottom_out_reg[1]_1 ;
  output [1:0]\bottom_out_reg[0]_0 ;
  input [2:0]DI;
  input [3:0]S;
  input [2:0]psum0_carry__0_i_4__4_0;
  input [2:0]psum0_carry__0_i_4__4_1;
  input [3:0]product__1_carry__0_i_5__7_0;
  input product__1_carry__0_0;
  input product__1_carry__0_1;
  input [0:0]SR;
  input [3:0]D;
  input CLK;

  wire CLK;
  wire [3:0]D;
  wire [2:0]DI;
  wire [7:0]Q;
  wire [3:0]S;
  wire [0:0]SR;
  wire [1:0]\bottom_out_reg[0]_0 ;
  wire [1:0]\bottom_out_reg[1]_0 ;
  wire [0:0]\bottom_out_reg[1]_1 ;
  wire \bottom_out_reg[2]_0 ;
  wire [1:0]\bottom_out_reg[2]_1 ;
  wire [3:0]\bottom_out_reg[3]_0 ;
  wire product__1_carry__0_0;
  wire product__1_carry__0_1;
  wire [3:0]product__1_carry__0_i_5__7_0;
  wire product__1_carry__0_i_8__7_n_0;
  wire product__1_carry__0_i_9__7_n_0;
  wire product__1_carry__0_n_0;
  wire product__1_carry__0_n_2;
  wire product__1_carry__0_n_3;
  wire product__1_carry__0_n_5;
  wire product__1_carry__0_n_6;
  wire product__1_carry__0_n_7;
  wire product__1_carry_n_0;
  wire product__1_carry_n_1;
  wire product__1_carry_n_2;
  wire product__1_carry_n_3;
  wire product__1_carry_n_4;
  wire product__1_carry_n_5;
  wire product__1_carry_n_6;
  wire product__1_carry_n_7;
  wire [7:0]psum0__4;
  wire psum0_carry__0_i_1__4_n_0;
  wire psum0_carry__0_i_2__4_n_0;
  wire psum0_carry__0_i_3__4_n_0;
  wire [2:0]psum0_carry__0_i_4__4_0;
  wire [2:0]psum0_carry__0_i_4__4_1;
  wire psum0_carry__0_i_4__4_n_0;
  wire psum0_carry__0_n_1;
  wire psum0_carry__0_n_2;
  wire psum0_carry__0_n_3;
  wire psum0_carry_i_1__4_n_0;
  wire psum0_carry_i_2__4_n_0;
  wire psum0_carry_i_3__4_n_0;
  wire psum0_carry_i_4__4_n_0;
  wire psum0_carry_n_0;
  wire psum0_carry_n_1;
  wire psum0_carry_n_2;
  wire psum0_carry_n_3;
  wire [2:2]NLW_product__1_carry__0_CO_UNCONNECTED;
  wire [3:3]NLW_product__1_carry__0_O_UNCONNECTED;
  wire [3:3]NLW_psum0_carry__0_CO_UNCONNECTED;

  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\bottom_out_reg[3]_0 [0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\bottom_out_reg[3]_0 [1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\bottom_out_reg[3]_0 [2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \bottom_out_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(\bottom_out_reg[3]_0 [3]),
        .R(SR));
  CARRY4 product__1_carry
       (.CI(1'b0),
        .CO({product__1_carry_n_0,product__1_carry_n_1,product__1_carry_n_2,product__1_carry_n_3}),
        .CYINIT(1'b0),
        .DI({DI,1'b0}),
        .O({product__1_carry_n_4,product__1_carry_n_5,product__1_carry_n_6,product__1_carry_n_7}),
        .S(S));
  CARRY4 product__1_carry__0
       (.CI(product__1_carry_n_0),
        .CO({product__1_carry__0_n_0,NLW_product__1_carry__0_CO_UNCONNECTED[2],product__1_carry__0_n_2,product__1_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,psum0_carry__0_i_4__4_0}),
        .O({NLW_product__1_carry__0_O_UNCONNECTED[3],product__1_carry__0_n_5,product__1_carry__0_n_6,product__1_carry__0_n_7}),
        .S({1'b1,psum0_carry__0_i_4__4_1}));
  LUT6 #(
    .INIT(64'hFC88800080000000)) 
    product__1_carry__0_i_1__7
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__7_0[3]),
        .I2(product__1_carry__0_i_5__7_0[1]),
        .I3(\bottom_out_reg[3]_0 [3]),
        .I4(\bottom_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__7_0[2]),
        .O(\bottom_out_reg[1]_0 [1]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    product__1_carry__0_i_3__7
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(\bottom_out_reg[3]_0 [1]),
        .I2(\bottom_out_reg[2]_0 ),
        .I3(product__1_carry__0_i_5__7_0[0]),
        .I4(product__1_carry__0_i_5__7_0[3]),
        .I5(product__1_carry__0_i_8__7_n_0),
        .O(\bottom_out_reg[1]_0 [0]));
  LUT4 #(
    .INIT(16'h7F80)) 
    product__1_carry__0_i_5__7
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_1),
        .I2(product__1_carry__0_i_5__7_0[3]),
        .I3(product__1_carry__0_i_9__7_n_0),
        .O(\bottom_out_reg[0]_0 [1]));
  LUT2 #(
    .INIT(4'h6)) 
    product__1_carry__0_i_6__7
       (.I0(\bottom_out_reg[1]_0 [0]),
        .I1(product__1_carry__0_0),
        .O(\bottom_out_reg[0]_0 [0]));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry__0_i_8__7
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__7_0[3]),
        .I2(\bottom_out_reg[3]_0 [2]),
        .I3(product__1_carry__0_i_5__7_0[2]),
        .I4(\bottom_out_reg[3]_0 [3]),
        .I5(product__1_carry__0_i_5__7_0[1]),
        .O(product__1_carry__0_i_8__7_n_0));
  LUT6 #(
    .INIT(64'hC4B470F04CCC8000)) 
    product__1_carry__0_i_9__7
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__7_0[3]),
        .I2(\bottom_out_reg[3]_0 [3]),
        .I3(product__1_carry__0_i_5__7_0[1]),
        .I4(\bottom_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__7_0[2]),
        .O(product__1_carry__0_i_9__7_n_0));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_2__7
       (.I0(\bottom_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__7_0[1]),
        .I2(product__1_carry__0_i_5__7_0[0]),
        .I3(\bottom_out_reg[3]_0 [2]),
        .O(\bottom_out_reg[1]_1 ));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_5__7
       (.I0(\bottom_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__7_0[0]),
        .I2(product__1_carry__0_i_5__7_0[1]),
        .I3(\bottom_out_reg[3]_0 [1]),
        .I4(\bottom_out_reg[3]_0 [0]),
        .I5(product__1_carry__0_i_5__7_0[2]),
        .O(\bottom_out_reg[2]_1 [1]));
  LUT4 #(
    .INIT(16'h7888)) 
    product__1_carry_i_6__7
       (.I0(\bottom_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_5__7_0[1]),
        .I2(\bottom_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__7_0[0]),
        .O(\bottom_out_reg[2]_1 [0]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_8__7
       (.I0(\bottom_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__7_0[1]),
        .O(\bottom_out_reg[2]_0 ));
  CARRY4 psum0_carry
       (.CI(1'b0),
        .CO({psum0_carry_n_0,psum0_carry_n_1,psum0_carry_n_2,psum0_carry_n_3}),
        .CYINIT(1'b0),
        .DI(Q[3:0]),
        .O(psum0__4[3:0]),
        .S({psum0_carry_i_1__4_n_0,psum0_carry_i_2__4_n_0,psum0_carry_i_3__4_n_0,psum0_carry_i_4__4_n_0}));
  CARRY4 psum0_carry__0
       (.CI(psum0_carry_n_0),
        .CO({NLW_psum0_carry__0_CO_UNCONNECTED[3],psum0_carry__0_n_1,psum0_carry__0_n_2,psum0_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,Q[6:4]}),
        .O(psum0__4[7:4]),
        .S({psum0_carry__0_i_1__4_n_0,psum0_carry__0_i_2__4_n_0,psum0_carry__0_i_3__4_n_0,psum0_carry__0_i_4__4_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_1__4
       (.I0(Q[7]),
        .I1(product__1_carry__0_n_0),
        .O(psum0_carry__0_i_1__4_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_2__4
       (.I0(Q[6]),
        .I1(product__1_carry__0_n_5),
        .O(psum0_carry__0_i_2__4_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_3__4
       (.I0(Q[5]),
        .I1(product__1_carry__0_n_6),
        .O(psum0_carry__0_i_3__4_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_4__4
       (.I0(Q[4]),
        .I1(product__1_carry__0_n_7),
        .O(psum0_carry__0_i_4__4_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_1__4
       (.I0(Q[3]),
        .I1(product__1_carry_n_4),
        .O(psum0_carry_i_1__4_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_2__4
       (.I0(Q[2]),
        .I1(product__1_carry_n_5),
        .O(psum0_carry_i_2__4_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_3__4
       (.I0(Q[1]),
        .I1(product__1_carry_n_6),
        .O(psum0_carry_i_3__4_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_4__4
       (.I0(Q[0]),
        .I1(product__1_carry_n_7),
        .O(psum0_carry_i_4__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__4[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__4[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__4[2]),
        .Q(Q[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__4[3]),
        .Q(Q[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__4[4]),
        .Q(Q[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__4[5]),
        .Q(Q[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__4[6]),
        .Q(Q[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__4[7]),
        .Q(Q[7]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "pe" *) 
module pe_5
   (Q,
    DI,
    \right_out_reg[3]_0 ,
    \right_out_reg[2]_0 ,
    \right_out_reg[3]_1 ,
    \right_out_reg[0]_0 ,
    S,
    \right_out_reg[2]_1 ,
    psum0_carry_i_4__5_0,
    psum0_carry_i_4__5_1,
    psum0_carry__0_i_4__5_0,
    psum0_carry__0_i_4__5_1,
    product__1_carry__0_i_5__6,
    product__1_carry_0,
    SR,
    D,
    CLK);
  output [7:0]Q;
  output [1:0]DI;
  output [3:0]\right_out_reg[3]_0 ;
  output \right_out_reg[2]_0 ;
  output [0:0]\right_out_reg[3]_1 ;
  output \right_out_reg[0]_0 ;
  output [1:0]S;
  output [0:0]\right_out_reg[2]_1 ;
  input [2:0]psum0_carry_i_4__5_0;
  input [3:0]psum0_carry_i_4__5_1;
  input [2:0]psum0_carry__0_i_4__5_0;
  input [2:0]psum0_carry__0_i_4__5_1;
  input [3:0]product__1_carry__0_i_5__6;
  input product__1_carry_0;
  input [0:0]SR;
  input [3:0]D;
  input CLK;

  wire CLK;
  wire [3:0]D;
  wire [1:0]DI;
  wire [7:0]Q;
  wire [1:0]S;
  wire [0:0]SR;
  wire product__1_carry_0;
  wire [3:0]product__1_carry__0_i_5__6;
  wire product__1_carry__0_n_0;
  wire product__1_carry__0_n_2;
  wire product__1_carry__0_n_3;
  wire product__1_carry__0_n_5;
  wire product__1_carry__0_n_6;
  wire product__1_carry__0_n_7;
  wire product__1_carry_n_0;
  wire product__1_carry_n_1;
  wire product__1_carry_n_2;
  wire product__1_carry_n_3;
  wire product__1_carry_n_4;
  wire product__1_carry_n_5;
  wire product__1_carry_n_6;
  wire product__1_carry_n_7;
  wire [7:0]psum0__5;
  wire psum0_carry__0_i_1__5_n_0;
  wire psum0_carry__0_i_2__5_n_0;
  wire psum0_carry__0_i_3__5_n_0;
  wire [2:0]psum0_carry__0_i_4__5_0;
  wire [2:0]psum0_carry__0_i_4__5_1;
  wire psum0_carry__0_i_4__5_n_0;
  wire psum0_carry__0_n_1;
  wire psum0_carry__0_n_2;
  wire psum0_carry__0_n_3;
  wire psum0_carry_i_1__5_n_0;
  wire psum0_carry_i_2__5_n_0;
  wire psum0_carry_i_3__5_n_0;
  wire [2:0]psum0_carry_i_4__5_0;
  wire [3:0]psum0_carry_i_4__5_1;
  wire psum0_carry_i_4__5_n_0;
  wire psum0_carry_n_0;
  wire psum0_carry_n_1;
  wire psum0_carry_n_2;
  wire psum0_carry_n_3;
  wire \right_out_reg[0]_0 ;
  wire \right_out_reg[2]_0 ;
  wire [0:0]\right_out_reg[2]_1 ;
  wire [3:0]\right_out_reg[3]_0 ;
  wire [0:0]\right_out_reg[3]_1 ;
  wire [2:2]NLW_product__1_carry__0_CO_UNCONNECTED;
  wire [3:3]NLW_product__1_carry__0_O_UNCONNECTED;
  wire [3:3]NLW_psum0_carry__0_CO_UNCONNECTED;

  CARRY4 product__1_carry
       (.CI(1'b0),
        .CO({product__1_carry_n_0,product__1_carry_n_1,product__1_carry_n_2,product__1_carry_n_3}),
        .CYINIT(1'b0),
        .DI({psum0_carry_i_4__5_0,1'b0}),
        .O({product__1_carry_n_4,product__1_carry_n_5,product__1_carry_n_6,product__1_carry_n_7}),
        .S(psum0_carry_i_4__5_1));
  CARRY4 product__1_carry__0
       (.CI(product__1_carry_n_0),
        .CO({product__1_carry__0_n_0,NLW_product__1_carry__0_CO_UNCONNECTED[2],product__1_carry__0_n_2,product__1_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,psum0_carry__0_i_4__5_0}),
        .O({NLW_product__1_carry__0_O_UNCONNECTED[3],product__1_carry__0_n_5,product__1_carry__0_n_6,product__1_carry__0_n_7}),
        .S({1'b1,psum0_carry__0_i_4__5_1}));
  LUT6 #(
    .INIT(64'hF880880080800000)) 
    product__1_carry__0_i_10__6
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__6[1]),
        .I2(\right_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__6[3]),
        .I4(product__1_carry__0_i_5__6[2]),
        .I5(\right_out_reg[3]_0 [0]),
        .O(\right_out_reg[2]_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    product__1_carry__0_i_2__6
       (.I0(\right_out_reg[3]_0 [3]),
        .I1(\right_out_reg[0]_0 ),
        .I2(product__1_carry__0_i_5__6[0]),
        .O(\right_out_reg[3]_1 ));
  LUT6 #(
    .INIT(64'h1777808088000000)) 
    product__1_carry__0_i_4__6
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__6[2]),
        .I2(\right_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__6[1]),
        .I4(\right_out_reg[3]_0 [3]),
        .I5(product__1_carry__0_i_5__6[3]),
        .O(\right_out_reg[2]_1 ));
  LUT6 #(
    .INIT(64'h8000200000000000)) 
    product__1_carry__0_i_7__6
       (.I0(\right_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_5__6[3]),
        .I2(product__1_carry__0_i_5__6[2]),
        .I3(\right_out_reg[3]_0 [1]),
        .I4(\right_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__6[1]),
        .O(\right_out_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_1__6
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__6[1]),
        .I2(product__1_carry__0_i_5__6[3]),
        .I3(\right_out_reg[3]_0 [0]),
        .I4(product__1_carry__0_i_5__6[2]),
        .I5(\right_out_reg[3]_0 [1]),
        .O(DI[1]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_3__6
       (.I0(\right_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__6[0]),
        .O(DI[0]));
  LUT6 #(
    .INIT(64'h95556AAA6AAA6AAA)) 
    product__1_carry_i_4__6
       (.I0(DI[1]),
        .I1(product__1_carry__0_i_5__6[1]),
        .I2(product__1_carry_0),
        .I3(\right_out_reg[3]_0 [0]),
        .I4(product__1_carry__0_i_5__6[0]),
        .I5(\right_out_reg[3]_0 [3]),
        .O(S[1]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_7__6
       (.I0(\right_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_5__6[0]),
        .O(S[0]));
  CARRY4 psum0_carry
       (.CI(1'b0),
        .CO({psum0_carry_n_0,psum0_carry_n_1,psum0_carry_n_2,psum0_carry_n_3}),
        .CYINIT(1'b0),
        .DI(Q[3:0]),
        .O(psum0__5[3:0]),
        .S({psum0_carry_i_1__5_n_0,psum0_carry_i_2__5_n_0,psum0_carry_i_3__5_n_0,psum0_carry_i_4__5_n_0}));
  CARRY4 psum0_carry__0
       (.CI(psum0_carry_n_0),
        .CO({NLW_psum0_carry__0_CO_UNCONNECTED[3],psum0_carry__0_n_1,psum0_carry__0_n_2,psum0_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,Q[6:4]}),
        .O(psum0__5[7:4]),
        .S({psum0_carry__0_i_1__5_n_0,psum0_carry__0_i_2__5_n_0,psum0_carry__0_i_3__5_n_0,psum0_carry__0_i_4__5_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_1__5
       (.I0(Q[7]),
        .I1(product__1_carry__0_n_0),
        .O(psum0_carry__0_i_1__5_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_2__5
       (.I0(Q[6]),
        .I1(product__1_carry__0_n_5),
        .O(psum0_carry__0_i_2__5_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_3__5
       (.I0(Q[5]),
        .I1(product__1_carry__0_n_6),
        .O(psum0_carry__0_i_3__5_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_4__5
       (.I0(Q[4]),
        .I1(product__1_carry__0_n_7),
        .O(psum0_carry__0_i_4__5_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_1__5
       (.I0(Q[3]),
        .I1(product__1_carry_n_4),
        .O(psum0_carry_i_1__5_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_2__5
       (.I0(Q[2]),
        .I1(product__1_carry_n_5),
        .O(psum0_carry_i_2__5_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_3__5
       (.I0(Q[1]),
        .I1(product__1_carry_n_6),
        .O(psum0_carry_i_3__5_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_4__5
       (.I0(Q[0]),
        .I1(product__1_carry_n_7),
        .O(psum0_carry_i_4__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__5[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__5[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__5[2]),
        .Q(Q[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__5[3]),
        .Q(Q[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__5[4]),
        .Q(Q[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__5[5]),
        .Q(Q[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__5[6]),
        .Q(Q[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__5[7]),
        .Q(Q[7]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\right_out_reg[3]_0 [0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\right_out_reg[3]_0 [1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\right_out_reg[3]_0 [2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(\right_out_reg[3]_0 [3]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "pe" *) 
module pe_6
   (Q,
    \right_out_reg[2]_0 ,
    \right_out_reg[3]_0 ,
    \right_out_reg[2]_1 ,
    \right_out_reg[3]_1 ,
    \right_out_reg[0]_0 ,
    \bottom_out_reg[1] ,
    \right_out_reg[2]_2 ,
    DI,
    S,
    psum0_carry__0_i_4__6_0,
    psum0_carry__0_i_4__6_1,
    product__1_carry__0_i_5__7,
    product__1_carry_0,
    SR,
    D,
    CLK);
  output [7:0]Q;
  output [1:0]\right_out_reg[2]_0 ;
  output [3:0]\right_out_reg[3]_0 ;
  output \right_out_reg[2]_1 ;
  output [0:0]\right_out_reg[3]_1 ;
  output \right_out_reg[0]_0 ;
  output [1:0]\bottom_out_reg[1] ;
  output [0:0]\right_out_reg[2]_2 ;
  input [2:0]DI;
  input [3:0]S;
  input [2:0]psum0_carry__0_i_4__6_0;
  input [2:0]psum0_carry__0_i_4__6_1;
  input [3:0]product__1_carry__0_i_5__7;
  input product__1_carry_0;
  input [0:0]SR;
  input [3:0]D;
  input CLK;

  wire CLK;
  wire [3:0]D;
  wire [2:0]DI;
  wire [7:0]Q;
  wire [3:0]S;
  wire [0:0]SR;
  wire [1:0]\bottom_out_reg[1] ;
  wire product__1_carry_0;
  wire [3:0]product__1_carry__0_i_5__7;
  wire product__1_carry__0_n_0;
  wire product__1_carry__0_n_2;
  wire product__1_carry__0_n_3;
  wire product__1_carry__0_n_5;
  wire product__1_carry__0_n_6;
  wire product__1_carry__0_n_7;
  wire product__1_carry_n_0;
  wire product__1_carry_n_1;
  wire product__1_carry_n_2;
  wire product__1_carry_n_3;
  wire product__1_carry_n_4;
  wire product__1_carry_n_5;
  wire product__1_carry_n_6;
  wire product__1_carry_n_7;
  wire [7:0]psum0__6;
  wire psum0_carry__0_i_1__6_n_0;
  wire psum0_carry__0_i_2__6_n_0;
  wire psum0_carry__0_i_3__6_n_0;
  wire [2:0]psum0_carry__0_i_4__6_0;
  wire [2:0]psum0_carry__0_i_4__6_1;
  wire psum0_carry__0_i_4__6_n_0;
  wire psum0_carry__0_n_1;
  wire psum0_carry__0_n_2;
  wire psum0_carry__0_n_3;
  wire psum0_carry_i_1__6_n_0;
  wire psum0_carry_i_2__6_n_0;
  wire psum0_carry_i_3__6_n_0;
  wire psum0_carry_i_4__6_n_0;
  wire psum0_carry_n_0;
  wire psum0_carry_n_1;
  wire psum0_carry_n_2;
  wire psum0_carry_n_3;
  wire \right_out_reg[0]_0 ;
  wire [1:0]\right_out_reg[2]_0 ;
  wire \right_out_reg[2]_1 ;
  wire [0:0]\right_out_reg[2]_2 ;
  wire [3:0]\right_out_reg[3]_0 ;
  wire [0:0]\right_out_reg[3]_1 ;
  wire [2:2]NLW_product__1_carry__0_CO_UNCONNECTED;
  wire [3:3]NLW_product__1_carry__0_O_UNCONNECTED;
  wire [3:3]NLW_psum0_carry__0_CO_UNCONNECTED;

  CARRY4 product__1_carry
       (.CI(1'b0),
        .CO({product__1_carry_n_0,product__1_carry_n_1,product__1_carry_n_2,product__1_carry_n_3}),
        .CYINIT(1'b0),
        .DI({DI,1'b0}),
        .O({product__1_carry_n_4,product__1_carry_n_5,product__1_carry_n_6,product__1_carry_n_7}),
        .S(S));
  CARRY4 product__1_carry__0
       (.CI(product__1_carry_n_0),
        .CO({product__1_carry__0_n_0,NLW_product__1_carry__0_CO_UNCONNECTED[2],product__1_carry__0_n_2,product__1_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,psum0_carry__0_i_4__6_0}),
        .O({NLW_product__1_carry__0_O_UNCONNECTED[3],product__1_carry__0_n_5,product__1_carry__0_n_6,product__1_carry__0_n_7}),
        .S({1'b1,psum0_carry__0_i_4__6_1}));
  LUT6 #(
    .INIT(64'hF880880080800000)) 
    product__1_carry__0_i_10__7
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__7[1]),
        .I2(\right_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__7[3]),
        .I4(product__1_carry__0_i_5__7[2]),
        .I5(\right_out_reg[3]_0 [0]),
        .O(\right_out_reg[2]_1 ));
  LUT3 #(
    .INIT(8'h80)) 
    product__1_carry__0_i_2__7
       (.I0(\right_out_reg[3]_0 [3]),
        .I1(\right_out_reg[0]_0 ),
        .I2(product__1_carry__0_i_5__7[0]),
        .O(\right_out_reg[3]_1 ));
  LUT6 #(
    .INIT(64'h1777808088000000)) 
    product__1_carry__0_i_4__7
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__7[2]),
        .I2(\right_out_reg[3]_0 [1]),
        .I3(product__1_carry__0_i_5__7[1]),
        .I4(\right_out_reg[3]_0 [3]),
        .I5(product__1_carry__0_i_5__7[3]),
        .O(\right_out_reg[2]_2 ));
  LUT6 #(
    .INIT(64'h8000200000000000)) 
    product__1_carry__0_i_7__7
       (.I0(\right_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_5__7[3]),
        .I2(product__1_carry__0_i_5__7[2]),
        .I3(\right_out_reg[3]_0 [1]),
        .I4(\right_out_reg[3]_0 [2]),
        .I5(product__1_carry__0_i_5__7[1]),
        .O(\right_out_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h8777788878887888)) 
    product__1_carry_i_1__7
       (.I0(\right_out_reg[3]_0 [2]),
        .I1(product__1_carry__0_i_5__7[1]),
        .I2(product__1_carry__0_i_5__7[3]),
        .I3(\right_out_reg[3]_0 [0]),
        .I4(product__1_carry__0_i_5__7[2]),
        .I5(\right_out_reg[3]_0 [1]),
        .O(\right_out_reg[2]_0 [1]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_3__7
       (.I0(\right_out_reg[3]_0 [1]),
        .I1(product__1_carry__0_i_5__7[0]),
        .O(\right_out_reg[2]_0 [0]));
  LUT6 #(
    .INIT(64'h95556AAA6AAA6AAA)) 
    product__1_carry_i_4__7
       (.I0(\right_out_reg[2]_0 [1]),
        .I1(product__1_carry__0_i_5__7[1]),
        .I2(product__1_carry_0),
        .I3(\right_out_reg[3]_0 [0]),
        .I4(product__1_carry__0_i_5__7[0]),
        .I5(\right_out_reg[3]_0 [3]),
        .O(\bottom_out_reg[1] [1]));
  LUT2 #(
    .INIT(4'h8)) 
    product__1_carry_i_7__7
       (.I0(\right_out_reg[3]_0 [0]),
        .I1(product__1_carry__0_i_5__7[0]),
        .O(\bottom_out_reg[1] [0]));
  CARRY4 psum0_carry
       (.CI(1'b0),
        .CO({psum0_carry_n_0,psum0_carry_n_1,psum0_carry_n_2,psum0_carry_n_3}),
        .CYINIT(1'b0),
        .DI(Q[3:0]),
        .O(psum0__6[3:0]),
        .S({psum0_carry_i_1__6_n_0,psum0_carry_i_2__6_n_0,psum0_carry_i_3__6_n_0,psum0_carry_i_4__6_n_0}));
  CARRY4 psum0_carry__0
       (.CI(psum0_carry_n_0),
        .CO({NLW_psum0_carry__0_CO_UNCONNECTED[3],psum0_carry__0_n_1,psum0_carry__0_n_2,psum0_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,Q[6:4]}),
        .O(psum0__6[7:4]),
        .S({psum0_carry__0_i_1__6_n_0,psum0_carry__0_i_2__6_n_0,psum0_carry__0_i_3__6_n_0,psum0_carry__0_i_4__6_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_1__6
       (.I0(Q[7]),
        .I1(product__1_carry__0_n_0),
        .O(psum0_carry__0_i_1__6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_2__6
       (.I0(Q[6]),
        .I1(product__1_carry__0_n_5),
        .O(psum0_carry__0_i_2__6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_3__6
       (.I0(Q[5]),
        .I1(product__1_carry__0_n_6),
        .O(psum0_carry__0_i_3__6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_4__6
       (.I0(Q[4]),
        .I1(product__1_carry__0_n_7),
        .O(psum0_carry__0_i_4__6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_1__6
       (.I0(Q[3]),
        .I1(product__1_carry_n_4),
        .O(psum0_carry_i_1__6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_2__6
       (.I0(Q[2]),
        .I1(product__1_carry_n_5),
        .O(psum0_carry_i_2__6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_3__6
       (.I0(Q[1]),
        .I1(product__1_carry_n_6),
        .O(psum0_carry_i_3__6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_4__6
       (.I0(Q[0]),
        .I1(product__1_carry_n_7),
        .O(psum0_carry_i_4__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__6[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__6[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__6[2]),
        .Q(Q[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__6[3]),
        .Q(Q[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__6[4]),
        .Q(Q[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__6[5]),
        .Q(Q[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__6[6]),
        .Q(Q[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(psum0__6[7]),
        .Q(Q[7]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\right_out_reg[3]_0 [0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\right_out_reg[3]_0 [1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\right_out_reg[3]_0 [2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \right_out_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(\right_out_reg[3]_0 [3]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "pe" *) 
module pe_7
   (Q,
    DI,
    S,
    psum0_carry__0_i_4__7_0,
    psum0_carry__0_i_4__7_1,
    rst,
    clk);
  output [7:0]Q;
  input [2:0]DI;
  input [3:0]S;
  input [2:0]psum0_carry__0_i_4__7_0;
  input [2:0]psum0_carry__0_i_4__7_1;
  input rst;
  input clk;

  wire [2:0]DI;
  wire [7:0]Q;
  wire [3:0]S;
  wire clk;
  wire product__1_carry__0_n_0;
  wire product__1_carry__0_n_2;
  wire product__1_carry__0_n_3;
  wire product__1_carry__0_n_5;
  wire product__1_carry__0_n_6;
  wire product__1_carry__0_n_7;
  wire product__1_carry_n_0;
  wire product__1_carry_n_1;
  wire product__1_carry_n_2;
  wire product__1_carry_n_3;
  wire product__1_carry_n_4;
  wire product__1_carry_n_5;
  wire product__1_carry_n_6;
  wire product__1_carry_n_7;
  wire [7:0]psum0__7;
  wire psum0_carry__0_i_1__7_n_0;
  wire psum0_carry__0_i_2__7_n_0;
  wire psum0_carry__0_i_3__7_n_0;
  wire [2:0]psum0_carry__0_i_4__7_0;
  wire [2:0]psum0_carry__0_i_4__7_1;
  wire psum0_carry__0_i_4__7_n_0;
  wire psum0_carry__0_n_1;
  wire psum0_carry__0_n_2;
  wire psum0_carry__0_n_3;
  wire psum0_carry_i_1__7_n_0;
  wire psum0_carry_i_2__7_n_0;
  wire psum0_carry_i_3__7_n_0;
  wire psum0_carry_i_4__7_n_0;
  wire psum0_carry_n_0;
  wire psum0_carry_n_1;
  wire psum0_carry_n_2;
  wire psum0_carry_n_3;
  wire rst;
  wire [2:2]NLW_product__1_carry__0_CO_UNCONNECTED;
  wire [3:3]NLW_product__1_carry__0_O_UNCONNECTED;
  wire [3:3]NLW_psum0_carry__0_CO_UNCONNECTED;

  CARRY4 product__1_carry
       (.CI(1'b0),
        .CO({product__1_carry_n_0,product__1_carry_n_1,product__1_carry_n_2,product__1_carry_n_3}),
        .CYINIT(1'b0),
        .DI({DI,1'b0}),
        .O({product__1_carry_n_4,product__1_carry_n_5,product__1_carry_n_6,product__1_carry_n_7}),
        .S(S));
  CARRY4 product__1_carry__0
       (.CI(product__1_carry_n_0),
        .CO({product__1_carry__0_n_0,NLW_product__1_carry__0_CO_UNCONNECTED[2],product__1_carry__0_n_2,product__1_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,psum0_carry__0_i_4__7_0}),
        .O({NLW_product__1_carry__0_O_UNCONNECTED[3],product__1_carry__0_n_5,product__1_carry__0_n_6,product__1_carry__0_n_7}),
        .S({1'b1,psum0_carry__0_i_4__7_1}));
  CARRY4 psum0_carry
       (.CI(1'b0),
        .CO({psum0_carry_n_0,psum0_carry_n_1,psum0_carry_n_2,psum0_carry_n_3}),
        .CYINIT(1'b0),
        .DI(Q[3:0]),
        .O(psum0__7[3:0]),
        .S({psum0_carry_i_1__7_n_0,psum0_carry_i_2__7_n_0,psum0_carry_i_3__7_n_0,psum0_carry_i_4__7_n_0}));
  CARRY4 psum0_carry__0
       (.CI(psum0_carry_n_0),
        .CO({NLW_psum0_carry__0_CO_UNCONNECTED[3],psum0_carry__0_n_1,psum0_carry__0_n_2,psum0_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,Q[6:4]}),
        .O(psum0__7[7:4]),
        .S({psum0_carry__0_i_1__7_n_0,psum0_carry__0_i_2__7_n_0,psum0_carry__0_i_3__7_n_0,psum0_carry__0_i_4__7_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_1__7
       (.I0(Q[7]),
        .I1(product__1_carry__0_n_0),
        .O(psum0_carry__0_i_1__7_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_2__7
       (.I0(Q[6]),
        .I1(product__1_carry__0_n_5),
        .O(psum0_carry__0_i_2__7_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_3__7
       (.I0(Q[5]),
        .I1(product__1_carry__0_n_6),
        .O(psum0_carry__0_i_3__7_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry__0_i_4__7
       (.I0(Q[4]),
        .I1(product__1_carry__0_n_7),
        .O(psum0_carry__0_i_4__7_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_1__7
       (.I0(Q[3]),
        .I1(product__1_carry_n_4),
        .O(psum0_carry_i_1__7_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_2__7
       (.I0(Q[2]),
        .I1(product__1_carry_n_5),
        .O(psum0_carry_i_2__7_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_3__7
       (.I0(Q[1]),
        .I1(product__1_carry_n_6),
        .O(psum0_carry_i_3__7_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    psum0_carry_i_4__7
       (.I0(Q[0]),
        .I1(product__1_carry_n_7),
        .O(psum0_carry_i_4__7_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(psum0__7[0]),
        .Q(Q[0]),
        .R(rst));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(psum0__7[1]),
        .Q(Q[1]),
        .R(rst));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(psum0__7[2]),
        .Q(Q[2]),
        .R(rst));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(psum0__7[3]),
        .Q(Q[3]),
        .R(rst));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(psum0__7[4]),
        .Q(Q[4]),
        .R(rst));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(psum0__7[5]),
        .Q(Q[5]),
        .R(rst));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(psum0__7[6]),
        .Q(Q[6]),
        .R(rst));
  FDRE #(
    .INIT(1'b0)) 
    \psum_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(psum0__7[7]),
        .Q(Q[7]),
        .R(rst));
endmodule

(* NotValidForBitStream *)
module systolic_array
   (clk,
    rst,
    \a_row[0] ,
    \a_row[1] ,
    \a_row[2] ,
    \b_col[0] ,
    \b_col[1] ,
    \b_col[2] ,
    \result[0][0] ,
    \result[0][1] ,
    \result[0][2] ,
    \result[1][0] ,
    \result[1][1] ,
    \result[1][2] ,
    \result[2][0] ,
    \result[2][1] ,
    \result[2][2] );
  input clk;
  input rst;
  input [3:0]\a_row[0] ;
  input [3:0]\a_row[1] ;
  input [3:0]\a_row[2] ;
  input [3:0]\b_col[0] ;
  input [3:0]\b_col[1] ;
  input [3:0]\b_col[2] ;
  output [7:0]\result[0][0] ;
  output [7:0]\result[0][1] ;
  output [7:0]\result[0][2] ;
  output [7:0]\result[1][0] ;
  output [7:0]\result[1][1] ;
  output [7:0]\result[1][2] ;
  output [7:0]\result[2][0] ;
  output [7:0]\result[2][1] ;
  output [7:0]\result[2][2] ;

  wire [3:0]\a_row[0] ;
  wire [3:0]\a_row[1] ;
  wire [3:0]\a_row[2] ;
  wire [3:0]\b_col[0] ;
  wire [3:0]\b_col[1] ;
  wire [3:0]\b_col[2] ;
  wire [3:0]bottom_out;
  wire \bottom_out_reg[0]_i_1__0_n_0 ;
  wire \bottom_out_reg[0]_i_1__1_n_0 ;
  wire \bottom_out_reg[0]_i_1_n_0 ;
  wire \bottom_out_reg[1]_i_1__0_n_0 ;
  wire \bottom_out_reg[1]_i_1__1_n_0 ;
  wire \bottom_out_reg[1]_i_1_n_0 ;
  wire \bottom_out_reg[2]_i_1__0_n_0 ;
  wire \bottom_out_reg[2]_i_1__1_n_0 ;
  wire \bottom_out_reg[2]_i_1_n_0 ;
  wire \bottom_out_reg[3]_i_1__0_n_0 ;
  wire \bottom_out_reg[3]_i_1__1_n_0 ;
  wire \bottom_out_reg[3]_i_1_n_0 ;
  wire clk;
  wire clk_IBUF;
  wire clk_IBUF_BUFG;
  wire [7:0]\result[0][0] ;
  wire [7:0]\result[0][0]_OBUF ;
  wire [7:0]\result[0][1] ;
  wire [7:0]\result[0][1]_OBUF ;
  wire [7:0]\result[0][2] ;
  wire [7:0]\result[0][2]_OBUF ;
  wire [7:0]\result[1][0] ;
  wire [7:0]\result[1][0]_OBUF ;
  wire [7:0]\result[1][1] ;
  wire [7:0]\result[1][1]_OBUF ;
  wire [7:0]\result[1][2] ;
  wire [7:0]\result[1][2]_OBUF ;
  wire [7:0]\result[2][0] ;
  wire [7:0]\result[2][0]_OBUF ;
  wire [7:0]\result[2][1] ;
  wire [7:0]\result[2][1]_OBUF ;
  wire [7:0]\result[2][2] ;
  wire [7:0]\result[2][2]_OBUF ;
  wire [3:0]right_out;
  wire \right_out_reg[0]_i_1__0_n_0 ;
  wire \right_out_reg[0]_i_1__1_n_0 ;
  wire \right_out_reg[0]_i_1_n_0 ;
  wire \right_out_reg[1]_i_1__0_n_0 ;
  wire \right_out_reg[1]_i_1__1_n_0 ;
  wire \right_out_reg[1]_i_1_n_0 ;
  wire \right_out_reg[2]_i_1__0_n_0 ;
  wire \right_out_reg[2]_i_1__1_n_0 ;
  wire \right_out_reg[2]_i_1_n_0 ;
  wire \right_out_reg[3]_i_1__0_n_0 ;
  wire \right_out_reg[3]_i_1__1_n_0 ;
  wire \right_out_reg[3]_i_1_n_0 ;
  wire \row[0].col[0].u_pe_n_12 ;
  wire \row[0].col[0].u_pe_n_13 ;
  wire \row[0].col[0].u_pe_n_14 ;
  wire \row[0].col[0].u_pe_n_15 ;
  wire \row[0].col[0].u_pe_n_16 ;
  wire \row[0].col[0].u_pe_n_17 ;
  wire \row[0].col[0].u_pe_n_18 ;
  wire \row[0].col[0].u_pe_n_19 ;
  wire \row[0].col[0].u_pe_n_20 ;
  wire \row[0].col[0].u_pe_n_21 ;
  wire \row[0].col[0].u_pe_n_26 ;
  wire \row[0].col[0].u_pe_n_27 ;
  wire \row[0].col[0].u_pe_n_28 ;
  wire \row[0].col[0].u_pe_n_29 ;
  wire \row[0].col[0].u_pe_n_30 ;
  wire \row[0].col[0].u_pe_n_31 ;
  wire \row[0].col[0].u_pe_n_32 ;
  wire \row[0].col[0].u_pe_n_33 ;
  wire \row[0].col[0].u_pe_n_34 ;
  wire \row[0].col[0].u_pe_n_35 ;
  wire \row[0].col[0].u_pe_n_36 ;
  wire \row[0].col[0].u_pe_n_37 ;
  wire \row[0].col[0].u_pe_n_38 ;
  wire \row[0].col[0].u_pe_n_39 ;
  wire \row[0].col[0].u_pe_n_40 ;
  wire \row[0].col[0].u_pe_n_41 ;
  wire \row[0].col[0].u_pe_n_42 ;
  wire \row[0].col[1].u_pe_n_0 ;
  wire \row[0].col[1].u_pe_n_10 ;
  wire \row[0].col[1].u_pe_n_11 ;
  wire \row[0].col[1].u_pe_n_12 ;
  wire \row[0].col[1].u_pe_n_13 ;
  wire \row[0].col[1].u_pe_n_14 ;
  wire \row[0].col[1].u_pe_n_15 ;
  wire \row[0].col[1].u_pe_n_16 ;
  wire \row[0].col[1].u_pe_n_17 ;
  wire \row[0].col[1].u_pe_n_18 ;
  wire \row[0].col[1].u_pe_n_19 ;
  wire \row[0].col[1].u_pe_n_20 ;
  wire \row[0].col[1].u_pe_n_21 ;
  wire \row[0].col[1].u_pe_n_22 ;
  wire \row[0].col[1].u_pe_n_23 ;
  wire \row[0].col[1].u_pe_n_24 ;
  wire \row[0].col[1].u_pe_n_25 ;
  wire \row[0].col[1].u_pe_n_26 ;
  wire \row[0].col[1].u_pe_n_27 ;
  wire \row[0].col[1].u_pe_n_28 ;
  wire \row[0].col[1].u_pe_n_29 ;
  wire \row[0].col[1].u_pe_n_30 ;
  wire \row[0].col[1].u_pe_n_31 ;
  wire \row[0].col[1].u_pe_n_32 ;
  wire \row[0].col[1].u_pe_n_33 ;
  wire \row[0].col[1].u_pe_n_9 ;
  wire \row[0].col[2].u_pe_n_10 ;
  wire \row[0].col[2].u_pe_n_11 ;
  wire \row[0].col[2].u_pe_n_12 ;
  wire \row[0].col[2].u_pe_n_13 ;
  wire \row[0].col[2].u_pe_n_14 ;
  wire \row[0].col[2].u_pe_n_15 ;
  wire \row[0].col[2].u_pe_n_16 ;
  wire \row[0].col[2].u_pe_n_17 ;
  wire \row[0].col[2].u_pe_n_18 ;
  wire \row[0].col[2].u_pe_n_19 ;
  wire \row[0].col[2].u_pe_n_8 ;
  wire \row[0].col[2].u_pe_n_9 ;
  wire \row[1].col[0].u_pe_n_10 ;
  wire \row[1].col[0].u_pe_n_11 ;
  wire \row[1].col[0].u_pe_n_12 ;
  wire \row[1].col[0].u_pe_n_13 ;
  wire \row[1].col[0].u_pe_n_14 ;
  wire \row[1].col[0].u_pe_n_15 ;
  wire \row[1].col[0].u_pe_n_16 ;
  wire \row[1].col[0].u_pe_n_17 ;
  wire \row[1].col[0].u_pe_n_18 ;
  wire \row[1].col[0].u_pe_n_19 ;
  wire \row[1].col[0].u_pe_n_20 ;
  wire \row[1].col[0].u_pe_n_21 ;
  wire \row[1].col[0].u_pe_n_22 ;
  wire \row[1].col[0].u_pe_n_23 ;
  wire \row[1].col[0].u_pe_n_24 ;
  wire \row[1].col[0].u_pe_n_25 ;
  wire \row[1].col[0].u_pe_n_26 ;
  wire \row[1].col[0].u_pe_n_27 ;
  wire \row[1].col[0].u_pe_n_28 ;
  wire \row[1].col[0].u_pe_n_29 ;
  wire \row[1].col[0].u_pe_n_30 ;
  wire \row[1].col[0].u_pe_n_31 ;
  wire \row[1].col[0].u_pe_n_32 ;
  wire \row[1].col[0].u_pe_n_8 ;
  wire \row[1].col[0].u_pe_n_9 ;
  wire \row[1].col[1].u_pe_n_10 ;
  wire \row[1].col[1].u_pe_n_11 ;
  wire \row[1].col[1].u_pe_n_12 ;
  wire \row[1].col[1].u_pe_n_13 ;
  wire \row[1].col[1].u_pe_n_14 ;
  wire \row[1].col[1].u_pe_n_15 ;
  wire \row[1].col[1].u_pe_n_16 ;
  wire \row[1].col[1].u_pe_n_17 ;
  wire \row[1].col[1].u_pe_n_18 ;
  wire \row[1].col[1].u_pe_n_19 ;
  wire \row[1].col[1].u_pe_n_20 ;
  wire \row[1].col[1].u_pe_n_21 ;
  wire \row[1].col[1].u_pe_n_22 ;
  wire \row[1].col[1].u_pe_n_23 ;
  wire \row[1].col[1].u_pe_n_24 ;
  wire \row[1].col[1].u_pe_n_25 ;
  wire \row[1].col[1].u_pe_n_26 ;
  wire \row[1].col[1].u_pe_n_27 ;
  wire \row[1].col[1].u_pe_n_28 ;
  wire \row[1].col[1].u_pe_n_29 ;
  wire \row[1].col[1].u_pe_n_30 ;
  wire \row[1].col[1].u_pe_n_31 ;
  wire \row[1].col[1].u_pe_n_8 ;
  wire \row[1].col[1].u_pe_n_9 ;
  wire \row[1].col[2].u_pe_n_10 ;
  wire \row[1].col[2].u_pe_n_11 ;
  wire \row[1].col[2].u_pe_n_12 ;
  wire \row[1].col[2].u_pe_n_13 ;
  wire \row[1].col[2].u_pe_n_14 ;
  wire \row[1].col[2].u_pe_n_15 ;
  wire \row[1].col[2].u_pe_n_16 ;
  wire \row[1].col[2].u_pe_n_17 ;
  wire \row[1].col[2].u_pe_n_18 ;
  wire \row[1].col[2].u_pe_n_19 ;
  wire \row[1].col[2].u_pe_n_8 ;
  wire \row[1].col[2].u_pe_n_9 ;
  wire \row[2].col[0].u_pe_n_10 ;
  wire \row[2].col[0].u_pe_n_11 ;
  wire \row[2].col[0].u_pe_n_12 ;
  wire \row[2].col[0].u_pe_n_13 ;
  wire \row[2].col[0].u_pe_n_14 ;
  wire \row[2].col[0].u_pe_n_15 ;
  wire \row[2].col[0].u_pe_n_16 ;
  wire \row[2].col[0].u_pe_n_17 ;
  wire \row[2].col[0].u_pe_n_18 ;
  wire \row[2].col[0].u_pe_n_19 ;
  wire \row[2].col[0].u_pe_n_8 ;
  wire \row[2].col[0].u_pe_n_9 ;
  wire \row[2].col[1].u_pe_n_10 ;
  wire \row[2].col[1].u_pe_n_11 ;
  wire \row[2].col[1].u_pe_n_12 ;
  wire \row[2].col[1].u_pe_n_13 ;
  wire \row[2].col[1].u_pe_n_14 ;
  wire \row[2].col[1].u_pe_n_15 ;
  wire \row[2].col[1].u_pe_n_16 ;
  wire \row[2].col[1].u_pe_n_17 ;
  wire \row[2].col[1].u_pe_n_18 ;
  wire \row[2].col[1].u_pe_n_19 ;
  wire \row[2].col[1].u_pe_n_8 ;
  wire \row[2].col[1].u_pe_n_9 ;
  wire rst;
  wire rst_IBUF;

  IBUF \bottom_out_reg[0]_i_1 
       (.I(\b_col[0] [0]),
        .O(\bottom_out_reg[0]_i_1_n_0 ));
  IBUF \bottom_out_reg[0]_i_1__0 
       (.I(\b_col[1] [0]),
        .O(\bottom_out_reg[0]_i_1__0_n_0 ));
  IBUF \bottom_out_reg[0]_i_1__1 
       (.I(\b_col[2] [0]),
        .O(\bottom_out_reg[0]_i_1__1_n_0 ));
  IBUF \bottom_out_reg[1]_i_1 
       (.I(\b_col[0] [1]),
        .O(\bottom_out_reg[1]_i_1_n_0 ));
  IBUF \bottom_out_reg[1]_i_1__0 
       (.I(\b_col[1] [1]),
        .O(\bottom_out_reg[1]_i_1__0_n_0 ));
  IBUF \bottom_out_reg[1]_i_1__1 
       (.I(\b_col[2] [1]),
        .O(\bottom_out_reg[1]_i_1__1_n_0 ));
  IBUF \bottom_out_reg[2]_i_1 
       (.I(\b_col[0] [2]),
        .O(\bottom_out_reg[2]_i_1_n_0 ));
  IBUF \bottom_out_reg[2]_i_1__0 
       (.I(\b_col[1] [2]),
        .O(\bottom_out_reg[2]_i_1__0_n_0 ));
  IBUF \bottom_out_reg[2]_i_1__1 
       (.I(\b_col[2] [2]),
        .O(\bottom_out_reg[2]_i_1__1_n_0 ));
  IBUF \bottom_out_reg[3]_i_1 
       (.I(\b_col[0] [3]),
        .O(\bottom_out_reg[3]_i_1_n_0 ));
  IBUF \bottom_out_reg[3]_i_1__0 
       (.I(\b_col[1] [3]),
        .O(\bottom_out_reg[3]_i_1__0_n_0 ));
  IBUF \bottom_out_reg[3]_i_1__1 
       (.I(\b_col[2] [3]),
        .O(\bottom_out_reg[3]_i_1__1_n_0 ));
  BUFG clk_IBUF_BUFG_inst
       (.I(clk_IBUF),
        .O(clk_IBUF_BUFG));
  IBUF clk_IBUF_inst
       (.I(clk),
        .O(clk_IBUF));
  OBUF \result[0][0][0]_INST_0 
       (.I(\result[0][0]_OBUF [0]),
        .O(\result[0][0] [0]));
  OBUF \result[0][0][1]_INST_0 
       (.I(\result[0][0]_OBUF [1]),
        .O(\result[0][0] [1]));
  OBUF \result[0][0][2]_INST_0 
       (.I(\result[0][0]_OBUF [2]),
        .O(\result[0][0] [2]));
  OBUF \result[0][0][3]_INST_0 
       (.I(\result[0][0]_OBUF [3]),
        .O(\result[0][0] [3]));
  OBUF \result[0][0][4]_INST_0 
       (.I(\result[0][0]_OBUF [4]),
        .O(\result[0][0] [4]));
  OBUF \result[0][0][5]_INST_0 
       (.I(\result[0][0]_OBUF [5]),
        .O(\result[0][0] [5]));
  OBUF \result[0][0][6]_INST_0 
       (.I(\result[0][0]_OBUF [6]),
        .O(\result[0][0] [6]));
  OBUF \result[0][0][7]_INST_0 
       (.I(\result[0][0]_OBUF [7]),
        .O(\result[0][0] [7]));
  OBUF \result[0][1][0]_INST_0 
       (.I(\result[0][1]_OBUF [0]),
        .O(\result[0][1] [0]));
  OBUF \result[0][1][1]_INST_0 
       (.I(\result[0][1]_OBUF [1]),
        .O(\result[0][1] [1]));
  OBUF \result[0][1][2]_INST_0 
       (.I(\result[0][1]_OBUF [2]),
        .O(\result[0][1] [2]));
  OBUF \result[0][1][3]_INST_0 
       (.I(\result[0][1]_OBUF [3]),
        .O(\result[0][1] [3]));
  OBUF \result[0][1][4]_INST_0 
       (.I(\result[0][1]_OBUF [4]),
        .O(\result[0][1] [4]));
  OBUF \result[0][1][5]_INST_0 
       (.I(\result[0][1]_OBUF [5]),
        .O(\result[0][1] [5]));
  OBUF \result[0][1][6]_INST_0 
       (.I(\result[0][1]_OBUF [6]),
        .O(\result[0][1] [6]));
  OBUF \result[0][1][7]_INST_0 
       (.I(\result[0][1]_OBUF [7]),
        .O(\result[0][1] [7]));
  OBUF \result[0][2][0]_INST_0 
       (.I(\result[0][2]_OBUF [0]),
        .O(\result[0][2] [0]));
  OBUF \result[0][2][1]_INST_0 
       (.I(\result[0][2]_OBUF [1]),
        .O(\result[0][2] [1]));
  OBUF \result[0][2][2]_INST_0 
       (.I(\result[0][2]_OBUF [2]),
        .O(\result[0][2] [2]));
  OBUF \result[0][2][3]_INST_0 
       (.I(\result[0][2]_OBUF [3]),
        .O(\result[0][2] [3]));
  OBUF \result[0][2][4]_INST_0 
       (.I(\result[0][2]_OBUF [4]),
        .O(\result[0][2] [4]));
  OBUF \result[0][2][5]_INST_0 
       (.I(\result[0][2]_OBUF [5]),
        .O(\result[0][2] [5]));
  OBUF \result[0][2][6]_INST_0 
       (.I(\result[0][2]_OBUF [6]),
        .O(\result[0][2] [6]));
  OBUF \result[0][2][7]_INST_0 
       (.I(\result[0][2]_OBUF [7]),
        .O(\result[0][2] [7]));
  OBUF \result[1][0][0]_INST_0 
       (.I(\result[1][0]_OBUF [0]),
        .O(\result[1][0] [0]));
  OBUF \result[1][0][1]_INST_0 
       (.I(\result[1][0]_OBUF [1]),
        .O(\result[1][0] [1]));
  OBUF \result[1][0][2]_INST_0 
       (.I(\result[1][0]_OBUF [2]),
        .O(\result[1][0] [2]));
  OBUF \result[1][0][3]_INST_0 
       (.I(\result[1][0]_OBUF [3]),
        .O(\result[1][0] [3]));
  OBUF \result[1][0][4]_INST_0 
       (.I(\result[1][0]_OBUF [4]),
        .O(\result[1][0] [4]));
  OBUF \result[1][0][5]_INST_0 
       (.I(\result[1][0]_OBUF [5]),
        .O(\result[1][0] [5]));
  OBUF \result[1][0][6]_INST_0 
       (.I(\result[1][0]_OBUF [6]),
        .O(\result[1][0] [6]));
  OBUF \result[1][0][7]_INST_0 
       (.I(\result[1][0]_OBUF [7]),
        .O(\result[1][0] [7]));
  OBUF \result[1][1][0]_INST_0 
       (.I(\result[1][1]_OBUF [0]),
        .O(\result[1][1] [0]));
  OBUF \result[1][1][1]_INST_0 
       (.I(\result[1][1]_OBUF [1]),
        .O(\result[1][1] [1]));
  OBUF \result[1][1][2]_INST_0 
       (.I(\result[1][1]_OBUF [2]),
        .O(\result[1][1] [2]));
  OBUF \result[1][1][3]_INST_0 
       (.I(\result[1][1]_OBUF [3]),
        .O(\result[1][1] [3]));
  OBUF \result[1][1][4]_INST_0 
       (.I(\result[1][1]_OBUF [4]),
        .O(\result[1][1] [4]));
  OBUF \result[1][1][5]_INST_0 
       (.I(\result[1][1]_OBUF [5]),
        .O(\result[1][1] [5]));
  OBUF \result[1][1][6]_INST_0 
       (.I(\result[1][1]_OBUF [6]),
        .O(\result[1][1] [6]));
  OBUF \result[1][1][7]_INST_0 
       (.I(\result[1][1]_OBUF [7]),
        .O(\result[1][1] [7]));
  OBUF \result[1][2][0]_INST_0 
       (.I(\result[1][2]_OBUF [0]),
        .O(\result[1][2] [0]));
  OBUF \result[1][2][1]_INST_0 
       (.I(\result[1][2]_OBUF [1]),
        .O(\result[1][2] [1]));
  OBUF \result[1][2][2]_INST_0 
       (.I(\result[1][2]_OBUF [2]),
        .O(\result[1][2] [2]));
  OBUF \result[1][2][3]_INST_0 
       (.I(\result[1][2]_OBUF [3]),
        .O(\result[1][2] [3]));
  OBUF \result[1][2][4]_INST_0 
       (.I(\result[1][2]_OBUF [4]),
        .O(\result[1][2] [4]));
  OBUF \result[1][2][5]_INST_0 
       (.I(\result[1][2]_OBUF [5]),
        .O(\result[1][2] [5]));
  OBUF \result[1][2][6]_INST_0 
       (.I(\result[1][2]_OBUF [6]),
        .O(\result[1][2] [6]));
  OBUF \result[1][2][7]_INST_0 
       (.I(\result[1][2]_OBUF [7]),
        .O(\result[1][2] [7]));
  OBUF \result[2][0][0]_INST_0 
       (.I(\result[2][0]_OBUF [0]),
        .O(\result[2][0] [0]));
  OBUF \result[2][0][1]_INST_0 
       (.I(\result[2][0]_OBUF [1]),
        .O(\result[2][0] [1]));
  OBUF \result[2][0][2]_INST_0 
       (.I(\result[2][0]_OBUF [2]),
        .O(\result[2][0] [2]));
  OBUF \result[2][0][3]_INST_0 
       (.I(\result[2][0]_OBUF [3]),
        .O(\result[2][0] [3]));
  OBUF \result[2][0][4]_INST_0 
       (.I(\result[2][0]_OBUF [4]),
        .O(\result[2][0] [4]));
  OBUF \result[2][0][5]_INST_0 
       (.I(\result[2][0]_OBUF [5]),
        .O(\result[2][0] [5]));
  OBUF \result[2][0][6]_INST_0 
       (.I(\result[2][0]_OBUF [6]),
        .O(\result[2][0] [6]));
  OBUF \result[2][0][7]_INST_0 
       (.I(\result[2][0]_OBUF [7]),
        .O(\result[2][0] [7]));
  OBUF \result[2][1][0]_INST_0 
       (.I(\result[2][1]_OBUF [0]),
        .O(\result[2][1] [0]));
  OBUF \result[2][1][1]_INST_0 
       (.I(\result[2][1]_OBUF [1]),
        .O(\result[2][1] [1]));
  OBUF \result[2][1][2]_INST_0 
       (.I(\result[2][1]_OBUF [2]),
        .O(\result[2][1] [2]));
  OBUF \result[2][1][3]_INST_0 
       (.I(\result[2][1]_OBUF [3]),
        .O(\result[2][1] [3]));
  OBUF \result[2][1][4]_INST_0 
       (.I(\result[2][1]_OBUF [4]),
        .O(\result[2][1] [4]));
  OBUF \result[2][1][5]_INST_0 
       (.I(\result[2][1]_OBUF [5]),
        .O(\result[2][1] [5]));
  OBUF \result[2][1][6]_INST_0 
       (.I(\result[2][1]_OBUF [6]),
        .O(\result[2][1] [6]));
  OBUF \result[2][1][7]_INST_0 
       (.I(\result[2][1]_OBUF [7]),
        .O(\result[2][1] [7]));
  OBUF \result[2][2][0]_INST_0 
       (.I(\result[2][2]_OBUF [0]),
        .O(\result[2][2] [0]));
  OBUF \result[2][2][1]_INST_0 
       (.I(\result[2][2]_OBUF [1]),
        .O(\result[2][2] [1]));
  OBUF \result[2][2][2]_INST_0 
       (.I(\result[2][2]_OBUF [2]),
        .O(\result[2][2] [2]));
  OBUF \result[2][2][3]_INST_0 
       (.I(\result[2][2]_OBUF [3]),
        .O(\result[2][2] [3]));
  OBUF \result[2][2][4]_INST_0 
       (.I(\result[2][2]_OBUF [4]),
        .O(\result[2][2] [4]));
  OBUF \result[2][2][5]_INST_0 
       (.I(\result[2][2]_OBUF [5]),
        .O(\result[2][2] [5]));
  OBUF \result[2][2][6]_INST_0 
       (.I(\result[2][2]_OBUF [6]),
        .O(\result[2][2] [6]));
  OBUF \result[2][2][7]_INST_0 
       (.I(\result[2][2]_OBUF [7]),
        .O(\result[2][2] [7]));
  IBUF \right_out_reg[0]_i_1 
       (.I(\a_row[0] [0]),
        .O(\right_out_reg[0]_i_1_n_0 ));
  IBUF \right_out_reg[0]_i_1__0 
       (.I(\a_row[1] [0]),
        .O(\right_out_reg[0]_i_1__0_n_0 ));
  IBUF \right_out_reg[0]_i_1__1 
       (.I(\a_row[2] [0]),
        .O(\right_out_reg[0]_i_1__1_n_0 ));
  IBUF \right_out_reg[1]_i_1 
       (.I(\a_row[0] [1]),
        .O(\right_out_reg[1]_i_1_n_0 ));
  IBUF \right_out_reg[1]_i_1__0 
       (.I(\a_row[1] [1]),
        .O(\right_out_reg[1]_i_1__0_n_0 ));
  IBUF \right_out_reg[1]_i_1__1 
       (.I(\a_row[2] [1]),
        .O(\right_out_reg[1]_i_1__1_n_0 ));
  IBUF \right_out_reg[2]_i_1 
       (.I(\a_row[0] [2]),
        .O(\right_out_reg[2]_i_1_n_0 ));
  IBUF \right_out_reg[2]_i_1__0 
       (.I(\a_row[1] [2]),
        .O(\right_out_reg[2]_i_1__0_n_0 ));
  IBUF \right_out_reg[2]_i_1__1 
       (.I(\a_row[2] [2]),
        .O(\right_out_reg[2]_i_1__1_n_0 ));
  IBUF \right_out_reg[3]_i_1 
       (.I(\a_row[0] [3]),
        .O(\right_out_reg[3]_i_1_n_0 ));
  IBUF \right_out_reg[3]_i_1__0 
       (.I(\a_row[1] [3]),
        .O(\right_out_reg[3]_i_1__0_n_0 ));
  IBUF \right_out_reg[3]_i_1__1 
       (.I(\a_row[2] [3]),
        .O(\right_out_reg[3]_i_1__1_n_0 ));
  pe \row[0].col[0].u_pe 
       (.CLK(clk_IBUF_BUFG),
        .CO(\row[0].col[1].u_pe_n_0 ),
        .DI({\row[0].col[0].u_pe_n_12 ,\row[0].col[0].u_pe_n_13 ,\row[0].col[0].u_pe_n_14 }),
        .Q(\result[0][0]_OBUF ),
        .S({\row[0].col[0].u_pe_n_18 ,\row[0].col[0].u_pe_n_19 ,\row[0].col[0].u_pe_n_20 ,\row[0].col[0].u_pe_n_21 }),
        .SR(rst_IBUF),
        .\bottom_out_reg[0]_0 (\bottom_out_reg[0]_i_1_n_0 ),
        .\bottom_out_reg[1]_0 ({\row[0].col[0].u_pe_n_26 ,\row[0].col[0].u_pe_n_27 ,\row[0].col[0].u_pe_n_28 }),
        .\bottom_out_reg[1]_1 ({\row[0].col[0].u_pe_n_29 ,\row[0].col[0].u_pe_n_30 ,\row[0].col[0].u_pe_n_31 }),
        .\bottom_out_reg[1]_2 ({\row[0].col[0].u_pe_n_32 ,\row[0].col[0].u_pe_n_33 ,\row[0].col[0].u_pe_n_34 ,\row[0].col[0].u_pe_n_35 }),
        .\bottom_out_reg[1]_3 (\bottom_out_reg[1]_i_1_n_0 ),
        .\bottom_out_reg[2]_0 ({\row[0].col[0].u_pe_n_40 ,\row[0].col[0].u_pe_n_41 ,\row[0].col[0].u_pe_n_42 }),
        .\bottom_out_reg[2]_1 (\bottom_out_reg[2]_i_1_n_0 ),
        .\bottom_out_reg[3]_0 (bottom_out),
        .\bottom_out_reg[3]_1 (\bottom_out_reg[3]_i_1_n_0 ),
        .product__1_carry_0(\bottom_out_reg[0]_i_1__0_n_0 ),
        .product__1_carry_1(\right_out_reg[1]_i_1__0_n_0 ),
        .product__1_carry_2(\right_out_reg[0]_i_1__0_n_0 ),
        .product__1_carry__0_0(\right_out_reg[3]_i_1__0_n_0 ),
        .product__1_carry__0_i_5__0_0(\bottom_out_reg[1]_i_1__0_n_0 ),
        .product__1_carry__0_i_5__0_1(\bottom_out_reg[2]_i_1__0_n_0 ),
        .product__1_carry__0_i_5__0_2(\bottom_out_reg[3]_i_1__0_n_0 ),
        .product__1_carry__0_i_5__2_0(\right_out_reg[2]_i_1__0_n_0 ),
        .\psum_reg[7]_0 (\row[0].col[0].u_pe_n_36 ),
        .\result[0][1] (\result[0][1]_OBUF [7]),
        .\right_out_reg[0]_0 (\right_out_reg[0]_i_1_n_0 ),
        .\right_out_reg[1]_0 (\right_out_reg[1]_i_1_n_0 ),
        .\right_out_reg[2]_0 ({\row[0].col[0].u_pe_n_37 ,\row[0].col[0].u_pe_n_38 ,\row[0].col[0].u_pe_n_39 }),
        .\right_out_reg[2]_1 (\right_out_reg[2]_i_1_n_0 ),
        .\right_out_reg[3]_0 (right_out),
        .\right_out_reg[3]_1 ({\row[0].col[0].u_pe_n_15 ,\row[0].col[0].u_pe_n_16 ,\row[0].col[0].u_pe_n_17 }),
        .\right_out_reg[3]_2 (\right_out_reg[3]_i_1_n_0 ));
  pe_0 \row[0].col[1].u_pe 
       (.CLK(clk_IBUF_BUFG),
        .CO(\row[0].col[1].u_pe_n_0 ),
        .D(right_out),
        .DI({\row[0].col[0].u_pe_n_12 ,\row[0].col[0].u_pe_n_13 ,\row[0].col[0].u_pe_n_14 }),
        .Q(\result[0][1]_OBUF ),
        .S({\row[0].col[0].u_pe_n_18 ,\row[0].col[0].u_pe_n_19 ,\row[0].col[0].u_pe_n_20 ,\row[0].col[0].u_pe_n_21 }),
        .SR(rst_IBUF),
        .\bottom_out_reg[0]_0 ({\row[0].col[1].u_pe_n_32 ,\row[0].col[1].u_pe_n_33 }),
        .\bottom_out_reg[1]_0 ({\row[0].col[1].u_pe_n_24 ,\row[0].col[1].u_pe_n_25 }),
        .\bottom_out_reg[1]_1 (\row[0].col[1].u_pe_n_31 ),
        .\bottom_out_reg[2]_0 (\row[0].col[1].u_pe_n_23 ),
        .\bottom_out_reg[2]_1 ({\row[0].col[1].u_pe_n_29 ,\row[0].col[1].u_pe_n_30 }),
        .\bottom_out_reg[3]_0 ({\row[0].col[1].u_pe_n_19 ,\row[0].col[1].u_pe_n_20 ,\row[0].col[1].u_pe_n_21 ,\row[0].col[1].u_pe_n_22 }),
        .\bottom_out_reg[3]_1 ({\bottom_out_reg[3]_i_1__0_n_0 ,\bottom_out_reg[2]_i_1__0_n_0 ,\bottom_out_reg[1]_i_1__0_n_0 ,\bottom_out_reg[0]_i_1__0_n_0 }),
        .product__1_carry_0(\bottom_out_reg[0]_i_1__1_n_0 ),
        .product__1_carry__0_0(\row[1].col[0].u_pe_n_14 ),
        .product__1_carry__0_1(\row[1].col[0].u_pe_n_16 ),
        .product__1_carry__0_i_5__1_0(\bottom_out_reg[1]_i_1__1_n_0 ),
        .product__1_carry__0_i_5__1_1(\bottom_out_reg[2]_i_1__1_n_0 ),
        .product__1_carry__0_i_5__1_2(\bottom_out_reg[3]_i_1__1_n_0 ),
        .product__1_carry__0_i_5__3_0({\row[1].col[0].u_pe_n_10 ,\row[1].col[0].u_pe_n_11 ,\row[1].col[0].u_pe_n_12 ,\row[1].col[0].u_pe_n_13 }),
        .psum0_carry__0_i_4__0_0({\row[0].col[0].u_pe_n_15 ,\row[0].col[0].u_pe_n_16 ,\row[0].col[0].u_pe_n_17 }),
        .psum0_carry__0_i_4__0_1({\row[0].col[0].u_pe_n_37 ,\row[0].col[0].u_pe_n_38 ,\row[0].col[0].u_pe_n_39 }),
        .\psum_reg[7]_0 (\row[0].col[0].u_pe_n_36 ),
        .\right_out_reg[0]_0 ({\row[0].col[1].u_pe_n_15 ,\row[0].col[1].u_pe_n_16 ,\row[0].col[1].u_pe_n_17 ,\row[0].col[1].u_pe_n_18 }),
        .\right_out_reg[2]_0 ({\row[0].col[1].u_pe_n_9 ,\row[0].col[1].u_pe_n_10 ,\row[0].col[1].u_pe_n_11 }),
        .\right_out_reg[2]_1 ({\row[0].col[1].u_pe_n_26 ,\row[0].col[1].u_pe_n_27 ,\row[0].col[1].u_pe_n_28 }),
        .\right_out_reg[3]_0 ({\row[0].col[1].u_pe_n_12 ,\row[0].col[1].u_pe_n_13 ,\row[0].col[1].u_pe_n_14 }));
  pe_1 \row[0].col[2].u_pe 
       (.CLK(clk_IBUF_BUFG),
        .D({\bottom_out_reg[3]_i_1__1_n_0 ,\bottom_out_reg[2]_i_1__1_n_0 ,\bottom_out_reg[1]_i_1__1_n_0 ,\bottom_out_reg[0]_i_1__1_n_0 }),
        .DI({\row[0].col[2].u_pe_n_13 ,\row[0].col[2].u_pe_n_14 }),
        .Q(\result[0][2]_OBUF ),
        .S({\row[0].col[2].u_pe_n_15 ,\row[0].col[2].u_pe_n_16 }),
        .SR(rst_IBUF),
        .\bottom_out_reg[0]_0 ({\row[0].col[2].u_pe_n_18 ,\row[0].col[2].u_pe_n_19 }),
        .\bottom_out_reg[1]_0 (\row[0].col[2].u_pe_n_17 ),
        .\bottom_out_reg[2]_0 (\row[0].col[2].u_pe_n_12 ),
        .\bottom_out_reg[3]_0 ({\row[0].col[2].u_pe_n_8 ,\row[0].col[2].u_pe_n_9 ,\row[0].col[2].u_pe_n_10 ,\row[0].col[2].u_pe_n_11 }),
        .product__1_carry__0_0(\row[1].col[1].u_pe_n_14 ),
        .product__1_carry__0_1(\row[1].col[1].u_pe_n_16 ),
        .product__1_carry__0_i_5__4_0({\row[1].col[1].u_pe_n_10 ,\row[1].col[1].u_pe_n_11 ,\row[1].col[1].u_pe_n_12 ,\row[1].col[1].u_pe_n_13 }),
        .psum0_carry__0_i_4__1_0({\row[0].col[1].u_pe_n_12 ,\row[0].col[1].u_pe_n_13 ,\row[0].col[1].u_pe_n_14 }),
        .psum0_carry__0_i_4__1_1({\row[0].col[1].u_pe_n_26 ,\row[0].col[1].u_pe_n_27 ,\row[0].col[1].u_pe_n_28 }),
        .psum0_carry_i_4__1_0({\row[0].col[1].u_pe_n_9 ,\row[0].col[1].u_pe_n_10 ,\row[0].col[1].u_pe_n_11 }),
        .psum0_carry_i_4__1_1({\row[0].col[1].u_pe_n_15 ,\row[0].col[1].u_pe_n_16 ,\row[0].col[1].u_pe_n_17 ,\row[0].col[1].u_pe_n_18 }));
  pe_2 \row[1].col[0].u_pe 
       (.CLK(clk_IBUF_BUFG),
        .D({\right_out_reg[3]_i_1__0_n_0 ,\right_out_reg[2]_i_1__0_n_0 ,\right_out_reg[1]_i_1__0_n_0 ,\right_out_reg[0]_i_1__0_n_0 }),
        .DI({\row[1].col[0].u_pe_n_8 ,\row[1].col[0].u_pe_n_9 }),
        .Q(\result[1][0]_OBUF ),
        .S({\row[1].col[0].u_pe_n_17 ,\row[1].col[0].u_pe_n_18 }),
        .SR(rst_IBUF),
        .\bottom_out_reg[1]_0 ({\row[1].col[0].u_pe_n_19 ,\row[1].col[0].u_pe_n_20 ,\row[1].col[0].u_pe_n_21 }),
        .\bottom_out_reg[1]_1 ({\row[1].col[0].u_pe_n_22 ,\row[1].col[0].u_pe_n_23 ,\row[1].col[0].u_pe_n_24 }),
        .\bottom_out_reg[1]_2 ({\row[1].col[0].u_pe_n_25 ,\row[1].col[0].u_pe_n_26 ,\row[1].col[0].u_pe_n_27 ,\row[1].col[0].u_pe_n_28 }),
        .\bottom_out_reg[2]_0 ({\row[1].col[0].u_pe_n_30 ,\row[1].col[0].u_pe_n_31 ,\row[1].col[0].u_pe_n_32 }),
        .\bottom_out_reg[3]_0 (bottom_out),
        .product__1_carry_0(\right_out_reg[1]_i_1__1_n_0 ),
        .product__1_carry_1(\right_out_reg[0]_i_1__1_n_0 ),
        .product__1_carry_2(\row[0].col[1].u_pe_n_23 ),
        .product__1_carry__0_0(\right_out_reg[3]_i_1__1_n_0 ),
        .product__1_carry__0_i_5__3({\row[0].col[1].u_pe_n_19 ,\row[0].col[1].u_pe_n_20 ,\row[0].col[1].u_pe_n_21 ,\row[0].col[1].u_pe_n_22 }),
        .product__1_carry__0_i_5__5_0(\right_out_reg[2]_i_1__1_n_0 ),
        .psum0_carry__0_i_4__2_0({\row[0].col[0].u_pe_n_29 ,\row[0].col[0].u_pe_n_30 ,\row[0].col[0].u_pe_n_31 }),
        .psum0_carry__0_i_4__2_1({\row[0].col[0].u_pe_n_40 ,\row[0].col[0].u_pe_n_41 ,\row[0].col[0].u_pe_n_42 }),
        .psum0_carry_i_4__2_0({\row[0].col[0].u_pe_n_26 ,\row[0].col[0].u_pe_n_27 ,\row[0].col[0].u_pe_n_28 }),
        .psum0_carry_i_4__2_1({\row[0].col[0].u_pe_n_32 ,\row[0].col[0].u_pe_n_33 ,\row[0].col[0].u_pe_n_34 ,\row[0].col[0].u_pe_n_35 }),
        .\right_out_reg[0]_0 (\row[1].col[0].u_pe_n_16 ),
        .\right_out_reg[2]_0 (\row[1].col[0].u_pe_n_14 ),
        .\right_out_reg[2]_1 (\row[1].col[0].u_pe_n_29 ),
        .\right_out_reg[3]_0 ({\row[1].col[0].u_pe_n_10 ,\row[1].col[0].u_pe_n_11 ,\row[1].col[0].u_pe_n_12 ,\row[1].col[0].u_pe_n_13 }),
        .\right_out_reg[3]_1 (\row[1].col[0].u_pe_n_15 ));
  pe_3 \row[1].col[1].u_pe 
       (.CLK(clk_IBUF_BUFG),
        .D({\row[1].col[0].u_pe_n_10 ,\row[1].col[0].u_pe_n_11 ,\row[1].col[0].u_pe_n_12 ,\row[1].col[0].u_pe_n_13 }),
        .DI({\row[1].col[0].u_pe_n_8 ,\row[0].col[1].u_pe_n_31 ,\row[1].col[0].u_pe_n_9 }),
        .Q(\result[1][1]_OBUF ),
        .S({\row[1].col[0].u_pe_n_17 ,\row[0].col[1].u_pe_n_29 ,\row[0].col[1].u_pe_n_30 ,\row[1].col[0].u_pe_n_18 }),
        .SR(rst_IBUF),
        .\bottom_out_reg[0]_0 ({\row[1].col[1].u_pe_n_30 ,\row[1].col[1].u_pe_n_31 }),
        .\bottom_out_reg[1]_0 ({\row[1].col[1].u_pe_n_17 ,\row[1].col[1].u_pe_n_18 }),
        .\bottom_out_reg[1]_1 ({\row[1].col[1].u_pe_n_24 ,\row[1].col[1].u_pe_n_25 }),
        .\bottom_out_reg[1]_2 (\row[1].col[1].u_pe_n_29 ),
        .\bottom_out_reg[2]_0 (\row[1].col[1].u_pe_n_23 ),
        .\bottom_out_reg[2]_1 ({\row[1].col[1].u_pe_n_27 ,\row[1].col[1].u_pe_n_28 }),
        .\bottom_out_reg[3]_0 ({\row[1].col[1].u_pe_n_19 ,\row[1].col[1].u_pe_n_20 ,\row[1].col[1].u_pe_n_21 ,\row[1].col[1].u_pe_n_22 }),
        .\bottom_out_reg[3]_1 ({\row[0].col[1].u_pe_n_19 ,\row[0].col[1].u_pe_n_20 ,\row[0].col[1].u_pe_n_21 ,\row[0].col[1].u_pe_n_22 }),
        .product__1_carry_0(\row[0].col[2].u_pe_n_12 ),
        .product__1_carry__0_0(\row[2].col[0].u_pe_n_14 ),
        .product__1_carry__0_1(\row[2].col[0].u_pe_n_16 ),
        .product__1_carry__0_i_5__4({\row[0].col[2].u_pe_n_8 ,\row[0].col[2].u_pe_n_9 ,\row[0].col[2].u_pe_n_10 ,\row[0].col[2].u_pe_n_11 }),
        .product__1_carry__0_i_5__6_0({\row[2].col[0].u_pe_n_10 ,\row[2].col[0].u_pe_n_11 ,\row[2].col[0].u_pe_n_12 ,\row[2].col[0].u_pe_n_13 }),
        .psum0_carry__0_i_4__3_0({\row[0].col[1].u_pe_n_24 ,\row[1].col[0].u_pe_n_15 ,\row[0].col[1].u_pe_n_25 }),
        .psum0_carry__0_i_4__3_1({\row[1].col[0].u_pe_n_29 ,\row[0].col[1].u_pe_n_32 ,\row[0].col[1].u_pe_n_33 }),
        .\right_out_reg[0]_0 (\row[1].col[1].u_pe_n_16 ),
        .\right_out_reg[2]_0 ({\row[1].col[1].u_pe_n_8 ,\row[1].col[1].u_pe_n_9 }),
        .\right_out_reg[2]_1 (\row[1].col[1].u_pe_n_14 ),
        .\right_out_reg[2]_2 (\row[1].col[1].u_pe_n_26 ),
        .\right_out_reg[3]_0 ({\row[1].col[1].u_pe_n_10 ,\row[1].col[1].u_pe_n_11 ,\row[1].col[1].u_pe_n_12 ,\row[1].col[1].u_pe_n_13 }),
        .\right_out_reg[3]_1 (\row[1].col[1].u_pe_n_15 ));
  pe_4 \row[1].col[2].u_pe 
       (.CLK(clk_IBUF_BUFG),
        .D({\row[0].col[2].u_pe_n_8 ,\row[0].col[2].u_pe_n_9 ,\row[0].col[2].u_pe_n_10 ,\row[0].col[2].u_pe_n_11 }),
        .DI({\row[1].col[1].u_pe_n_8 ,\row[0].col[2].u_pe_n_17 ,\row[1].col[1].u_pe_n_9 }),
        .Q(\result[1][2]_OBUF ),
        .S({\row[1].col[1].u_pe_n_17 ,\row[0].col[2].u_pe_n_15 ,\row[0].col[2].u_pe_n_16 ,\row[1].col[1].u_pe_n_18 }),
        .SR(rst_IBUF),
        .\bottom_out_reg[0]_0 ({\row[1].col[2].u_pe_n_18 ,\row[1].col[2].u_pe_n_19 }),
        .\bottom_out_reg[1]_0 ({\row[1].col[2].u_pe_n_13 ,\row[1].col[2].u_pe_n_14 }),
        .\bottom_out_reg[1]_1 (\row[1].col[2].u_pe_n_17 ),
        .\bottom_out_reg[2]_0 (\row[1].col[2].u_pe_n_12 ),
        .\bottom_out_reg[2]_1 ({\row[1].col[2].u_pe_n_15 ,\row[1].col[2].u_pe_n_16 }),
        .\bottom_out_reg[3]_0 ({\row[1].col[2].u_pe_n_8 ,\row[1].col[2].u_pe_n_9 ,\row[1].col[2].u_pe_n_10 ,\row[1].col[2].u_pe_n_11 }),
        .product__1_carry__0_0(\row[2].col[1].u_pe_n_14 ),
        .product__1_carry__0_1(\row[2].col[1].u_pe_n_16 ),
        .product__1_carry__0_i_5__7_0({\row[2].col[1].u_pe_n_10 ,\row[2].col[1].u_pe_n_11 ,\row[2].col[1].u_pe_n_12 ,\row[2].col[1].u_pe_n_13 }),
        .psum0_carry__0_i_4__4_0({\row[0].col[2].u_pe_n_13 ,\row[1].col[1].u_pe_n_15 ,\row[0].col[2].u_pe_n_14 }),
        .psum0_carry__0_i_4__4_1({\row[1].col[1].u_pe_n_26 ,\row[0].col[2].u_pe_n_18 ,\row[0].col[2].u_pe_n_19 }));
  pe_5 \row[2].col[0].u_pe 
       (.CLK(clk_IBUF_BUFG),
        .D({\right_out_reg[3]_i_1__1_n_0 ,\right_out_reg[2]_i_1__1_n_0 ,\right_out_reg[1]_i_1__1_n_0 ,\right_out_reg[0]_i_1__1_n_0 }),
        .DI({\row[2].col[0].u_pe_n_8 ,\row[2].col[0].u_pe_n_9 }),
        .Q(\result[2][0]_OBUF ),
        .S({\row[2].col[0].u_pe_n_17 ,\row[2].col[0].u_pe_n_18 }),
        .SR(rst_IBUF),
        .product__1_carry_0(\row[1].col[1].u_pe_n_23 ),
        .product__1_carry__0_i_5__6({\row[1].col[1].u_pe_n_19 ,\row[1].col[1].u_pe_n_20 ,\row[1].col[1].u_pe_n_21 ,\row[1].col[1].u_pe_n_22 }),
        .psum0_carry__0_i_4__5_0({\row[1].col[0].u_pe_n_22 ,\row[1].col[0].u_pe_n_23 ,\row[1].col[0].u_pe_n_24 }),
        .psum0_carry__0_i_4__5_1({\row[1].col[0].u_pe_n_30 ,\row[1].col[0].u_pe_n_31 ,\row[1].col[0].u_pe_n_32 }),
        .psum0_carry_i_4__5_0({\row[1].col[0].u_pe_n_19 ,\row[1].col[0].u_pe_n_20 ,\row[1].col[0].u_pe_n_21 }),
        .psum0_carry_i_4__5_1({\row[1].col[0].u_pe_n_25 ,\row[1].col[0].u_pe_n_26 ,\row[1].col[0].u_pe_n_27 ,\row[1].col[0].u_pe_n_28 }),
        .\right_out_reg[0]_0 (\row[2].col[0].u_pe_n_16 ),
        .\right_out_reg[2]_0 (\row[2].col[0].u_pe_n_14 ),
        .\right_out_reg[2]_1 (\row[2].col[0].u_pe_n_19 ),
        .\right_out_reg[3]_0 ({\row[2].col[0].u_pe_n_10 ,\row[2].col[0].u_pe_n_11 ,\row[2].col[0].u_pe_n_12 ,\row[2].col[0].u_pe_n_13 }),
        .\right_out_reg[3]_1 (\row[2].col[0].u_pe_n_15 ));
  pe_6 \row[2].col[1].u_pe 
       (.CLK(clk_IBUF_BUFG),
        .D({\row[2].col[0].u_pe_n_10 ,\row[2].col[0].u_pe_n_11 ,\row[2].col[0].u_pe_n_12 ,\row[2].col[0].u_pe_n_13 }),
        .DI({\row[2].col[0].u_pe_n_8 ,\row[1].col[1].u_pe_n_29 ,\row[2].col[0].u_pe_n_9 }),
        .Q(\result[2][1]_OBUF ),
        .S({\row[2].col[0].u_pe_n_17 ,\row[1].col[1].u_pe_n_27 ,\row[1].col[1].u_pe_n_28 ,\row[2].col[0].u_pe_n_18 }),
        .SR(rst_IBUF),
        .\bottom_out_reg[1] ({\row[2].col[1].u_pe_n_17 ,\row[2].col[1].u_pe_n_18 }),
        .product__1_carry_0(\row[1].col[2].u_pe_n_12 ),
        .product__1_carry__0_i_5__7({\row[1].col[2].u_pe_n_8 ,\row[1].col[2].u_pe_n_9 ,\row[1].col[2].u_pe_n_10 ,\row[1].col[2].u_pe_n_11 }),
        .psum0_carry__0_i_4__6_0({\row[1].col[1].u_pe_n_24 ,\row[2].col[0].u_pe_n_15 ,\row[1].col[1].u_pe_n_25 }),
        .psum0_carry__0_i_4__6_1({\row[2].col[0].u_pe_n_19 ,\row[1].col[1].u_pe_n_30 ,\row[1].col[1].u_pe_n_31 }),
        .\right_out_reg[0]_0 (\row[2].col[1].u_pe_n_16 ),
        .\right_out_reg[2]_0 ({\row[2].col[1].u_pe_n_8 ,\row[2].col[1].u_pe_n_9 }),
        .\right_out_reg[2]_1 (\row[2].col[1].u_pe_n_14 ),
        .\right_out_reg[2]_2 (\row[2].col[1].u_pe_n_19 ),
        .\right_out_reg[3]_0 ({\row[2].col[1].u_pe_n_10 ,\row[2].col[1].u_pe_n_11 ,\row[2].col[1].u_pe_n_12 ,\row[2].col[1].u_pe_n_13 }),
        .\right_out_reg[3]_1 (\row[2].col[1].u_pe_n_15 ));
  pe_7 \row[2].col[2].u_pe 
       (.DI({\row[2].col[1].u_pe_n_8 ,\row[1].col[2].u_pe_n_17 ,\row[2].col[1].u_pe_n_9 }),
        .Q(\result[2][2]_OBUF ),
        .S({\row[2].col[1].u_pe_n_17 ,\row[1].col[2].u_pe_n_15 ,\row[1].col[2].u_pe_n_16 ,\row[2].col[1].u_pe_n_18 }),
        .clk(clk_IBUF_BUFG),
        .psum0_carry__0_i_4__7_0({\row[1].col[2].u_pe_n_13 ,\row[2].col[1].u_pe_n_15 ,\row[1].col[2].u_pe_n_14 }),
        .psum0_carry__0_i_4__7_1({\row[2].col[1].u_pe_n_19 ,\row[1].col[2].u_pe_n_18 ,\row[1].col[2].u_pe_n_19 }),
        .rst(rst_IBUF));
  IBUF rst_IBUF_inst
       (.I(rst),
        .O(rst_IBUF));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
